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Recent Progress in Downsizing FeFETs for Fe-NAND Application

Published online by Cambridge University Press:  28 June 2011

Le Van Hai
Affiliation:
National Institute of Advanced Industrial Science and Technology, Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki, 305-8568, Japan
Mitsue Takahashi
Affiliation:
National Institute of Advanced Industrial Science and Technology, Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki, 305-8568, Japan
Shigeki Sakai
Affiliation:
National Institute of Advanced Industrial Science and Technology, Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki, 305-8568, Japan
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Abstract

Sub-micrometer ferroelectric-gate field-effect transistors (FeFETs) of 0.56 μm and 0.50 μm gate lengths were successfully fabricated for Fe-NAND cells. Gate stacks of the FeFETs were Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. The gate stacks were formed by electron beam lithography and inductively coupled plasma reactive ion etching (ICP-RIE). Ti and SiO2 hard masks were used for the 0.56 μm- and 0.50 μm-gate FeFETs, respectively, in the ICP-RIE process. Steep SBT sidewalls with the angle of 85° were obtained by using the SiO2 hard masks while 76° sidewalls were shown using Ti hard masks. All fabricated FeFETs showed good electrical characteristics. Drain current hysteresis showed larger memory windows than 0.95 V when the gate voltages were swung between 1±5 V. The FeFETs showed stable endurance behaviors over 108 program/erase cycles. Drain current retention properties of the FeFETs were good so that the drain current on/off ratios did not show practical changes after 3 days.

Type
Research Article
Copyright
Copyright © Materials Research Society 2011

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