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Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics

Published online by Cambridge University Press:  01 February 2011

Yatin Mutha
Affiliation:
Department of Electrical Engineering, Indian Institute of Technology, Bombay, Powai, Mumbai-400 076, India.
K.N. ManjulaRani
Affiliation:
Department of Electrical Engineering, Indian Institute of Technology, Bombay, Powai, Mumbai-400 076, India.
Rakesh Lal
Affiliation:
Department of Electrical Engineering, Indian Institute of Technology, Bombay, Powai, Mumbai-400 076, India.
V.Ramgopal Rao
Affiliation:
Department of Electrical Engineering, Indian Institute of Technology, Bombay, Powai, Mumbai-400 076, India.
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Abstract

We have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

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References

[1] Lai, S. K.Two carrier nature of interface state generation in hole trapping and radiation damageAppl. Phys. Lett., vol. 39, p.58 (1981).CrossRefGoogle Scholar
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[3] Mahapatra, S., Rao, V. Ramgopal, Manjularani, K.N. Parikh, C.D. Vasi, J. Cheng, B. Khare, M. and Woo, J.C.S. “100 nm Channel Length MNSFETs using a Jet Vapor Deposited Ultra-thin Silicon Nitride Gate Dielectric”, Technical Digest, 1999 Symposium on VLSI Technology, June 14-19, Kyoto, Japan Google Scholar
[4] Ma, T. P.Making silicon nitride film as a viable gate dielectric.” IEEE Trans Electron Dev 45(3) March 1998 pp 680690.CrossRefGoogle Scholar
[5] Mahapatra, S. Rao, V. Ramgopal, Cheng, B. Khare, M. Parikh, C. D. Woo, J. C. S. and Vasi, J.Performance and Hot-Carrier Reliability of 100 nm Channel Length Jet Vapor Deposited Si3N4 MNSFETs”, IEEE Transactions on Electron Devices, vol.48, (no.4), April 2001. p.679–84CrossRefGoogle Scholar

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