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A New Device Model of Amorphous Silicon Thin-Film Transistor for Circuit Simulation

Published online by Cambridge University Press:  21 February 2011

Hong S. Choi
Affiliation:
GoldStar Co., LTD., R&D Complex, An-Yang 430–080, Korea
Jin S. Park
Affiliation:
Seoul Nat'l. Univ., Dept. of Electrical Eng., Kwanak—Ku, Seoul 151–742, Korea
Chang H. Oh
Affiliation:
GoldStar Co., LTD., R&D Complex, An-Yang 430–080, Korea
In S. Joo
Affiliation:
Seoul Nat'l. Univ., Dept. of Electrical Eng., Kwanak—Ku, Seoul 151–742, Korea
Yong S. Kim
Affiliation:
Seoul Nat'l. Univ., Dept. of Electrical Eng., Kwanak—Ku, Seoul 151–742, Korea
Min K. Han
Affiliation:
Seoul Nat'l. Univ., Dept. of Electrical Eng., Kwanak—Ku, Seoul 151–742, Korea
Yearn I. Choi
Affiliation:
Ajou Univ., Dept. of Electronics Eng., Suwon 440–749, Korea
Jung G. Yun
Affiliation:
GoldStar Co., LTD., R&D Complex, An-Yang 430–080, Korea
Won K. Park
Affiliation:
GoldStar Co., LTD., R&D Complex, An-Yang 430–080, Korea
Woo Y. Kim
Affiliation:
GoldStar Co., LTD., R&D Complex, An-Yang 430–080, Korea
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Abstract

We present a new analytical model of amorphous silicon thin-film transistor (a-Si TFT) suitable for circuit simulators such as SPICE. The effects of localized gap state distributions of a-Si as well as temperatures on the a-Si TFT performances have been fully considered in the presented model. The parameters used in SPICE, such as transconductance, channel-length modulation, and power factor of source-drain current, are evaluated from the measured current-voltage and capacitance-voltage characteristics by employing the proposed extraction method. It has been found out that the analytical model is in good agreement with experimental data at both room temperature and elevated temperature and successfully implemented in a widely used circuit simulator.

Type
Research Article
Copyright
Copyright © Materials Research Society 1991

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References

[1] lto, H., Nishimura, Y., Nobue, M., Fuse, M., Nakamura, T., Ozawa, T., Tomiyama, S., Weisfield, R., Tuan, H.C., and Thompson, M.J., IEDM Tech. Digest, Washington, D.C. Dec. (1985).Google Scholar
[2] Thompson, M.J. and Tuan, H.C., IEDM Tech. Digest, Los Angeles, Dec. (1986).Google Scholar
[3] Morizono, M., SID 90 Digest, Las Vegas, May (1990).Google Scholar
[4] Tuinenga, P.W., SPICE:A Guide Circuit Simulation & Analysis Using Pspice. (Prentice Hall, New Jersey, 1988).Google Scholar
[5] Shur, M. and Hack, M., J. Appl. Phys. 55 (10) 3831 (1984).CrossRefGoogle Scholar
[6] Powell, M.J., IEEE Trans. Electron. Devices ED-36 (12) 2753 (1989).CrossRefGoogle Scholar
[7] Choi, H.S., Park, J.S., Oh, C.H., Han, M.K., and Choi, Y.I., Trans, of Korean Institute of Electrical Engineers, 1991 (to be published).Google Scholar
[8] Lustig, N. and Kanicki, J., J. Appl. Phys. 65 (10) 3951 (1989).CrossRefGoogle Scholar
Meyer, J.E., RCA Rev. 32 42 (1971).Google Scholar

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