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Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects

Published online by Cambridge University Press:  01 February 2011

Xiaopeng Xu
Affiliation:
xxu@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700 E. Middlefield Rd, Mountain View, Caliafornia, 94043, United States
Dipu Pramanik
Affiliation:
dpramani@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700 E. Middlefield Rd, Mountain View, CA, 94043, United States
Greg Rollins
Affiliation:
rollins@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700 E. Middlefield Rd, Mountain View, CA, 94043, United States
Corresponding
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Abstract

The layout dependence of process stress in Cu/low k interconnects are examined using various stress sources and layout patterns. The anisotropic grain growth stress model is compared with the conventional isotropic intrinsic stress model and the latter is found to underestimate stress concentrations in the dielectric regions near metal line ends. Both the grain growth stress in copper and the thermal mismatch stress in copper and low k dielectrics are considered in the layout dependence study. The results demonstrate that accurate stress evaluation in interconnect structures has to employ geometrical models that include layout variations. Capabilities are developed to extract these geometrical models directly from layout analysis.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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References

1 Lloyd, J. R., Lane, M. R., Liu, X. H., et al, Microelectronics Reliab., Vol 44, 2004, pp1835.Google Scholar
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3 Synopsys Process-Aware DFMTM tool suite manuals, 2006.Google Scholar
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6 Joo, Y. C., Paik, J. M., and Jung, J. K., MRS Proc. Vol. 863, 2005, pp. B7.6.1–B7.6.12.CrossRefGoogle Scholar

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