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Modeling Evolution of Temperature, Stress, Defects, and Dopant Diffusion in Silicon During Spike and Millisecond Annealing

Published online by Cambridge University Press:  01 February 2011

Victor Moroz
Affiliation:
victorm@synopsys.com, Synopsys, TCAD, 700 East Middlefield Road, Mountain View, CA, 94043, United States
Ignacio Martin-Bragado
Affiliation:
nacho@synopsys.com, Synopsys, Mountain View, CA, 94043, United States
Nikolas Zographos
Affiliation:
zograph@synopsys.com, Synopsys, Zurich, N/A, Switzerland
Dmitri Matveev
Affiliation:
matveev@synopsys.com, Synopsys, Zurich, N/A, Switzerland
Christoph Zechner
Affiliation:
zechner@synopsys.com, Synopsys, Zurich, N/A, Switzerland
Munkang Choi
Affiliation:
munkangc@synopsys.com, Synopsys, Mountain View, CA, 94043, United States
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Abstract

The bulk CMOS devices continue as the dominant player for at least another couple of technology nodes. This drives the increasingly contradicting requirements for the channel, source/drain extension, and heavily doped source/drain doping profiles. To analyze and optimize the transistors, it is becoming necessary to combine a number of effects that have been treated as decoupled so far. The temperature gradients, combined with stress engineering techniques such as embedded SiGe and Si:C source/drain and stress memorization technique, create non-uniform stress distributions determined by the layout patterns. The interaction of implant-induced damage with dopants, stress, and defect traps shapes up the dopant activation, retention of useful stress, and junction leakage. This work reviews recent trends in modeling these effects using continuum and kinetic Monte Carlo methods.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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References

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Modeling Evolution of Temperature, Stress, Defects, and Dopant Diffusion in Silicon During Spike and Millisecond Annealing
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