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A Method for Die Thickness Reduction to sub-35 μm

Published online by Cambridge University Press:  01 February 2011

Jeffrey Thompson
Affiliation:
j.thompson@draper.com, C.S Draper Laboratory, Microsystems Integration, Cambridge, Massachusetts, United States
Gary Tepolt
Affiliation:
gtepolt@draper.com, C.S Draper Laboratory, Microsystems Integration, Cambridge, Massachusetts, United States
Livia Racz
Affiliation:
lracz@draper.com, C.S Draper Laboratory, Microsystems Integration, Cambridge, Massachusetts, United States
Chris Rogers
Affiliation:
crogers@tufts.edu, Tufts University, Mechanical Engineering, Medford, Massachusetts, United States
Vincent Manno
Affiliation:
R.White@tufts.edu, Tufts Universtiy, Mechanical Engineering, Meford, Massachusetts, United States
Robert White
Affiliation:
vincent.manno@tufts.edu, Tufts University, Mechanical Engineering, Medford, Massachusetts, United States
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Abstract

Significant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to 35 μm thickness. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 μm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to 35 μm with ± 1.5 μm total thickness variation (TTV).

Keywords

Type
Research Article
Copyright
Copyright © Materials Research Society 2009

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References

[1] B.H Yeung, Hause, V., Lee, T., “Assessment of backside processes through die strength evaluation,” IEEE Transactions on Advanced Packaging, vol. 23, no. 3, Aug. 2000, pp. 582587.Google Scholar
[2] Pinel, S., Tasselli, J., Bailbe, J.P., Marty, A., Puech, P., and Esteve, D., “Mechanical lapping of ultra-thin wafers for 3D integration,” Proceedings of the IEEE 22nd International Conference on Microelectronics, vol. 2, May 2000, pp. 443446.Google Scholar
[3] Arunasalam, P., Gordon, M., and Schaper, L., “A systematic approach to thinning silicon wafers to the sub-40 μm thickness range,” J. Micro. Elect. Pack., vol. 3, 2006, pp. 8694.Google Scholar
[4] Vlahakis, J. et al., “In-situ measurement of the coefficient of friction and drag forces during chemical mechanical planarization”, Proceedings of the 11th International Conference on Chemical-Mechanical Polish (CMP) Planarization for ULSI Multilevel Interconnection (CMP-MIC) February, 2006, Fremont, California.Google Scholar

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