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Low Leakage Current Patterned Polymeric Transistors with PAG Assisted Cross-linking PVP as Gate Dielectric and Passivation Layers

Published online by Cambridge University Press:  01 February 2011

Cheng-Chin Liu
Affiliation:
jamchin.liu@msa.hinet.net, National Chiao Tung University, Electronics Engineering, 1001 Ta-Hsueh Road Hsinchu, Taiwan 30050, R.O.C, Hsinchu, 300, Taiwan, 886-03-571-5507, 886-03-572-4361
Kuo-Jui Chang
Affiliation:
kuojuichang@mail.nctu.edu.tw, National Chiao Tung University, Electronics Engineering, 1001 Ta-Hsueh Road Hsinchu, Hsinchu, 30050, Taiwan
Feng-Yu Yang
Affiliation:
FengYuYang@ITRI.ORG.TW, Industrial Technology Research Institute, Materials and Chemical Research Laboratories, 195 Chung-Hsing Road.Sec.4 Chu Tung, Hsinchu, 31050, Taiwan
Ta-Chuan Liao
Affiliation:
tcliao.ee92g@nctu.edu.tw, National Chiao Tung University, Electronics Engineering, 1001 Ta-Hsueh Road Hsinchu, Hsinchu, 30050, Taiwan
Huang-Chung Cheng
Affiliation:
hccheng536@mail.nctu.edu.tw, National Chiao Tung University, Electronics Engineering, 1001 Ta-Hsueh Road Hsinchu, Hsinchu, 30050, Taiwan
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Abstract

We have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (∼1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×104 and good subthreshold swing 1.66 V/decade.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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