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Lanthanum Oxide Capping Layer for Solution-Processed Ferroelectric-Gate Thin-Film Transistors

Published online by Cambridge University Press:  08 July 2011

Tue T. Phan ,
Trinh N. Q. Bui ,
Takaaki Miyasako ,
Thanh V. Pham ,
Eisuke Tokumitsu  and
Tatsuya Shimoda
Tue T. Phan
Affiliation:
School of Materials Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan.
Trinh N. Q. Bui
Affiliation:
Japan Science and Technology Agency, ERATO, Shimoda Nano-Liquid Process Project, 2-5-3 Asahidai, Nomi, Ishikawa 923-1211, Japan.
Takaaki Miyasako
Affiliation:
Japan Science and Technology Agency, ERATO, Shimoda Nano-Liquid Process Project, 2-5-3 Asahidai, Nomi, Ishikawa 923-1211, Japan.
Thanh V. Pham
Affiliation:
School of Materials Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan.
Eisuke Tokumitsu
Affiliation:
Japan Science and Technology Agency, ERATO, Shimoda Nano-Liquid Process Project, 2-5-3 Asahidai, Nomi, Ishikawa 923-1211, Japan. Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259-R2-19 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan.
Tatsuya Shimoda
Affiliation:
School of Materials Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan. Japan Science and Technology Agency, ERATO, Shimoda Nano-Liquid Process Project, 2-5-3 Asahidai, Nomi, Ishikawa 923-1211, Japan.
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Abstract

We report on the use of La2O3 (LO) as a capping layer for ferroelectric-gate thin-film transistors (FGTs) with solution-processed indium-tin-oxide (ITO) channel and Pb(Zr,Ti)O3 (PZT) gate insulator. The fabricated FGT exhibited excellent performance with a high “ON/OFF” current ratio (ION/IOFF) and a large memory window (∆Vth) of about 108 and 3.5 V, respectively. Additionally, a significantly improved data retention time (more than 16 hours) as compared to the ITO/PZT structure was also obtained as a result of good interface properties between the ITO channel and LO/PZT stacked gate insulator. We suggest that the LO capping layer acts as a barrier to prevent the interdiffusion and provides atomically flat ITO/LO/PZT interface. This all-oxide FGT device is very promising for future ferroelectric memories.

Keywords

ferroelectricmemorysolution deposition
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1337: Symposium Q – New Functional Materials and Emerging Device Architectures for Nonvolatile Memories , 2011 , mrss11-1337-q02-05
Copyright
Copyright © Materials Research Society 2011

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References

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