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Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

Published online by Cambridge University Press:  01 February 2011

Aditya Karmarkar
Affiliation:
adityap@synopsys.com, Synopsys (India) Pvt. Ltd., TCAD DFM Solutions, My Home Tycoon, 4th Floor, Block A, Begumpet, Hyderabad, 500016, India, +91-40-40222560, +91-40-23412517
Xiaopeng Xu
Affiliation:
Xiaopeng.Xu@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road,, Mountain View, CA, 94043, United States
Dipu Pramanik
Affiliation:
dpramani@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road,, Mountain View, CA, 94043, United States
Xi-Wei Lin
Affiliation:
Xi-Wei.Lin@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road, Mountain View, CA, 94043, United States
Greg Rollins
Affiliation:
Greg.Rollins@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road, Mountain View, CA, 94043, United States
Xiao Lin
Affiliation:
Xiao.Lin@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road, Mountain View, CA, 94043, United States
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Abstract

The industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low-k interconnects. The effects of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnect structures are examined and the reliability impact of mechanical stress is assessed.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

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Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability
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