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High Yield Polymer MEMS Process for CMOS/MEMS Integration

Published online by Cambridge University Press:  20 January 2011

Prasenjit Ray
Affiliation:
Centre of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.
V. Seena
Affiliation:
Centre of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.
Prakash R. Apte
Affiliation:
Centre of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.
Ramgopal Rao
Affiliation:
Centre of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.
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Abstract

MEMS community is increasingly using SU-8 as a structural material because it is self-patternable, compliant and needs a low thermal budget. While the exposed layers act as the structural layers, the unexposed SU-8 layers can act as the sacrificial layers, thus making it similar to a surface micromachining process. A sequence of exposed and unexposed SU-8 layers should lead to the development of a SU-8 based MEMS chip integrated with a pre-processed CMOS wafer. A process consisting of optical lithography to obtain SU-8 structures on a CMOS wafer is described in this paper.

Type
Research Article
Copyright
Copyright © Materials Research Society 2011

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