Skip to main content Accessibility help
×
Home
Hostname: page-component-79b67bcb76-4whtl Total loading time: 0.217 Render date: 2021-05-15T18:47:38.236Z Has data issue: true Feature Flags: { "shouldUseShareProductTool": true, "shouldUseHypothesis": true, "isUnsiloEnabled": true, "metricsAbstractViews": false, "figures": false, "newCiteModal": false, "newCitedByModal": true, "newEcommerce": true }

Fabrication and Evaluation of 3D Packages with Through Hole Via

Published online by Cambridge University Press:  26 February 2011

Dong Min Jang
Affiliation:
kkok78@kaist.ac.kr, KAIST, MS&E, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of, 82-42-869-4274, 82-42-869-8840
Kwang Yong Lee
Affiliation:
leeky97@hanmail.net, Hongik University, CEPM, Mapogu Sangsudong 72-1, Seoul, 121-791, Korea, Republic of
Chung Hyun Ryu
Affiliation:
sdomain@eeinfo.kaist.ac.kr, KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Byeong Hoon Cho
Affiliation:
cbh@kaist.ac.kr, KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Tae Sung Oh
Affiliation:
ohts@hongik.ac.kr, Hongik University, CEPM, Mapogu Sangsudong 72-1, Seoul, 121-791, Korea, Republic of
Joung Ho Kim
Affiliation:
joungho@ee.kaist.ac.kr, KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Won Jong Lee
Affiliation:
wjlee@kaist.ac.kr, KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Jin Yu
Affiliation:
jinyu@kaist.ac.kr, KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Get access

Abstract

System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated.

A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below.

References

1. Al-Sarawi, S. F., Abbott, D., and Franzon, P. D., IEEE Trans. CPMT. 21B, 2 (1988)Google Scholar
2. Sheng, S., Chandrakasan, A., and Brodersen, R. W., IEEE Commun. Mag. 30, 64 (1992)10.1109/35.210358CrossRefGoogle Scholar
3. Terrill, R. E., Proc. 1995 Int. Conf. Multichip Modules, Denver, CO, 711 (1995)Google Scholar
4. Crowley, R., “Three-dimensional electronics packaging", Tech. Rep., Techsearch Int. Inc. Austin, TX, 159161 (1993)Google Scholar
5. Ehrmann, O., Buschick, K., Chmiel, G., and Pareds, A., Proc. Int. Conf. Multichip Modules, Denver, CO (1995)Google Scholar
6. Kanbach, H., Wilde, J., Kriebel, F., and Meusel, E., Int. Conf. on High Density Packaging and MCMs, 248253 (1999)Google Scholar
7. Karnezos, M., Carson, F. and Pendse, R., “3D packaging promises performance, reliability gains with small footprints and lower profiles", Chip Scale Review (2005)Google Scholar
8. Takahashi, K., Terao, H., Tomita, Y., Yamaji, Y., Hoshino, M., Sato, T., Morifuji, T., Sunohara, M. and Bonkohara, M., Jpn. J. Appl. Phys. 40, 3032 (2001)10.1143/JJAP.40.3032CrossRefGoogle Scholar
9. Matsumoto, T., “Three-dimensional integration technology based on wafer bonding technique using micro-bumps", Ext. Abstr. Int. Conf. Solid State Devices Mater. Osaka., Japan, 1073–1073 (1995)Google Scholar
10. Ramm, P., Microelectron. Eng. 37, 39 (1997)CrossRefGoogle Scholar
11. Lee, K. Y., Lee, Y. H., Kim, Y. H., and Oh, T. S., J. Kor. Inst. Met. Mater. 43, 248 (2005)Google Scholar

Send article to Kindle

To send this article to your Kindle, first ensure no-reply@cambridge.org is added to your Approved Personal Document E-mail List under your Personal Document Settings on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part of your Kindle email address below. Find out more about sending to your Kindle. Find out more about sending to your Kindle.

Note you can select to send to either the @free.kindle.com or @kindle.com variations. ‘@free.kindle.com’ emails are free but can only be sent to your device when it is connected to wi-fi. ‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.

Find out more about the Kindle Personal Document Service.

Fabrication and Evaluation of 3D Packages with Through Hole Via
Available formats
×

Send article to Dropbox

To send this article to your Dropbox account, please select one or more formats and confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your <service> account. Find out more about sending content to Dropbox.

Fabrication and Evaluation of 3D Packages with Through Hole Via
Available formats
×

Send article to Google Drive

To send this article to your Google Drive account, please select one or more formats and confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your <service> account. Find out more about sending content to Google Drive.

Fabrication and Evaluation of 3D Packages with Through Hole Via
Available formats
×
×

Reply to: Submit a response


Your details


Conflicting interests

Do you have any conflicting interests? *