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Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology

Published online by Cambridge University Press:  01 February 2011

Abhisek Dixit
Affiliation:
Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai-400 076, India.
Rajiv O. Dusane
Affiliation:
Department of Metallurgical Engineering and Materials Science, Indian Institute of Technology Bombay, Powai, Mumbai-400 076, India.
V. Ramgopal Rao
Affiliation:
Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai-400 076, India.
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Abstract

Degrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

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References

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