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Effects of Thinned Multi-Stacked Wafer Thickness on Stress Distribution in the Wafer-on-a-Wafer (WOW) Structure

Published online by Cambridge University Press:  31 January 2011

Hideki Kitada
Affiliation:
Kitada@jp.fujitsu.com, University of Tokyo, Tokyo, Japan
Nobuyuki Maeda
Affiliation:
nmaeda@disco.co.jp, University of Tokyo, Tokyo, Japan
Koji Fujimoto
Affiliation:
Fujimoto-K4@mail.dnp.co.jp, University of Tokyo, Tokyo, Japan
Kousuke Suzuki
Affiliation:
Suzuki-K47@mail.dnp.co.jp, Dai Nippon Printing, Chiba, Japan
Tomoji Nakamura
Affiliation:
tomo.nakamura@jp.fujitsu.com, Fujitsu Laboratories Ltd, Kanagawa, Japan
Takayuki Ohba
Affiliation:
ohba@ducr.u-tokyo.ac.jp, University of Tokyo, Tokyo, Japan
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Abstract

In the trough silicon via (TSV) structure for 3-dimensional integration (3DI), large thermal-mechanical stress acts in the TSV caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. In this study, the stress of multi-stacked thin silicon wafers composed of copper TSV and copper/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of TSV of 3D-IC. The results of sensitivity analysis using design of experiment (DOE) indicated that the thickness of the silicon and adhesive layer are the key factors for the structural integration of TSV design.

Type
Research Article
Copyright
Copyright © Materials Research Society 2009

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References

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Effects of Thinned Multi-Stacked Wafer Thickness on Stress Distribution in the Wafer-on-a-Wafer (WOW) Structure
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