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The Effect of Rapid Thermal Processing on the Electrical Characteristics of Polysilicon Gate Mos Capacitors

Published online by Cambridge University Press:  28 February 2011

Susan B. Felch
Affiliation:
Varian Research Center, 611 Hansen Way, Palo Alto, CA 94303
David T. Hodul
Affiliation:
Varian Research Center, 611 Hansen Way, Palo Alto, CA 94303
Mak Salimian Mak Salimian
Affiliation:
Varian Research Center, 611 Hansen Way, Palo Alto, CA 94303
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Abstract

Rapid thermal processing has previously been observed to affect the dielectric integrity of thin oxides.' In order to study this phenomenon in more detail, we have fabricated a set of wafers with 290 Å thick gate oxide and patterned pads of 2000 Å thick doped polysilicon. Some of the pads were patterned with a wet etch, while others were dry etched in a commercial reactive ion etcher (RIE), which is suspected to be a damaging process. To simulate a self-aligned MOS process, some of the patterned wafers were also ion implanted with 70 keV, 2E15 As+/cm2 . Subsequently, all of the wafers were rapidly annealed in a Varian RTP-800 lamp annealer under a variety of conditions (lO00-1100°C, 10-30 sec), and the breakdown characteristics of the MOS capacitors were measured. A few control samples were annealed in a furnace. It was found that the rapid annealing cycle without ion implantation or dry etching caused no deterioration of the oxide quality. However, rapid annealing after either RIE or implantation does result in oxide breakdowns at lower voltages, with those capacitors having higher perimeter-toarea ratios affected to a greater degree. The effect of capacitor shape and annealing conditions on breakdown statistics and uniformity will be presented and discussed in light of possible ion bombardment damage during RIE and oxide charging during ion implantation. Several mechanisms explaining the breakdown properties will be discussed.

Type
Research Article
Copyright
Copyright © Materials Research Society 1987

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References

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