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Development of 3D-Packaging Process Technology for Stacked Memory Chips

Published online by Cambridge University Press:  26 February 2011

Toshiro Mitsuhashi
Affiliation:
mitsuhashi663@oki.com, Oki Electric Industry Co., Ltd., SIP Engineering Department, 550-1 Higashiasakawa, Hachioji, Tokyo, 192-0912, Japan
Yoshimi Egawa
Affiliation:
egawa252@oki.com, Oki Electric Industry, SIP Engineering Department, 550-1 Higashiasakawa, Hachioji, Tokyo, 192-0912, Japan
Osamu Kato
Affiliation:
katoh293@oki.com, Oki Electric Industry, SIP Engineering Department, 550-1 Higashiasakawa, Hachioji, Tokyo, 192-0912, Japan
Yoshihiro Saeki
Affiliation:
saeki328@oki.com, Oki Electric Industry, SIP Engineering Department, 550-1 Higashiasakawa, Hachioji, Tokyo, 192-0912, Japan
Hidekazu Kikuchi
Affiliation:
kikuchi476@oki.com, Oki Electric Industry, SIP Engineering Department, 550-1 Higashiasakawa, Hachioji, Tokyo, 192-0912, Japan
Shiro Uchiyama
Affiliation:
uchiyama-shiro@elpida.com, Elpida Memory, Kanagawa, N/A, Japan
Kayoko Shibata
Affiliation:
shibata-kayoko@elpida.com, Elpida Memory, Kanagawa, N/A, Japan
Junji Yamada
Affiliation:
yamada-junji@elpida.com, Elpida Memory, Kanagawa, N/A, Japan
Masakazu Ishino
Affiliation:
ishino-masakazu@elpida.com, Elpida Memory, Kanagawa, N/A, Japan
Hiroaki Ikeda
Affiliation:
ikeda-hiroaki@elpida.com, Elpida Memory, Kanagawa, N/A, Japan
Nobuaki Takahashi
Affiliation:
n.takahashi@necel.com, NEC Electronics, Kanagawa, N/A, Japan
Yoichiro Kurita
Affiliation:
y.kurita@necel.com, NEC Electronics, Kanagawa, N/A, Japan
Masahiro Komuro
Affiliation:
masahiro.komuro@necel.com, NEC Electronics, Kanagawa, N/A, Japan
Satoshi Matsui
Affiliation:
s.matsui@necel.com, NEC Electronics, Kanagawa, N/A, Japan
Masaya Kawano
Affiliation:
masaya.kawano@necel.com, NEC Electronics, Kanagawa, N/A, Japan
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Abstract

A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

1. Takahashi, Kenji et al., “Process Integration of 3D Chip Stack with Vertical Interconnection” in Proc. 2004Electronic Components and Technology Conference, pp. 601609 Google Scholar
2. Garrou, Philip, “3D Integration: A Status Report” in Proc. 3D Architectures for Semiconductor Integration and Packaging, Tempe, Arizona, June, 2005 Google Scholar
3. Ikeda, H., Kawano, M. and Mitsuhashi, T., “Stacked Memory Chip Technology Development”, SEMI Technology Symposium (STS) 2005 Proceedings, Session 9 pp. 3742.Google Scholar

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