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Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits

Published online by Cambridge University Press:  01 February 2011

Aleksandar Radisic
Affiliation:
Alex.Radisic@imec.beradialexa@yahoo.com, IMEC, Leuven, Belgium
Ole Lühn
Affiliation:
Ole.Luhn@imec.be, IMEC, Leuven, Belgium
Bart Swinnen
Affiliation:
Bart.Swinnen@imec.be, IMEC, Leuven, Belgium
Hugo Bender
Affiliation:
Hugo.Bender@imec.be, IMEC, Leuven, Belgium
Chris Drijbooms
Affiliation:
Christel.Drijbooms@imec.be, IMEC, Leuven, Belgium
Geert Doumen
Affiliation:
Geert.Doumen@imec.be, IMEC, Leuven, Belgium
Kristof Kellens
Affiliation:
Kristof.Kellens@imec.be, IMEC, Leuven, Belgium
Wouter Ruythooren
Affiliation:
Wouter.Ruythooren@imec.be, IMEC, Leuven, Belgium
Philippe M. Vereecken
Affiliation:
Philippe.Vereecken@imec.be, IMEC, Leuven, Belgium
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Abstract

Establishing a cost-effective technology for the metallization of through-Si vias (TSV) is an important factor in the realization and volume manufacturing of 3D-stacked integrated circuits (3D-SIC). Cu electroplating, which is the preferred technique, should provide not only a void-free TSV fill, but also short filling time and small overburden. The duration of the plating process is a significant contributor to the overall 3D process cost, and thus needs to be minimized. The overburden, the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the following processing steps (e.g. chemical mechanical polishing, CMP). In this paper we report on Cu plating of TSV-s with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits.

Type
Research Article
Copyright
Copyright © Materials Research Society 2009

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References

REFERENCES

1. Lühn, O., Celis, J.-P., Van Hoof, C., Baert, K., and Ruythooren, W., ECS Transactions, 6 (8), 2007, 123133.CrossRefGoogle Scholar
2. Lühn, O., Radisic, A., Vereecken, P. M., Swinnen, B., Van Hoof, C., Ruythooren, W., Celis, J.-P., Proc. Electronic Components and Technology Conference (ECTC), 58th, Lake Buena Vista, 27-30 May, pp. 866870, 2008.Google Scholar
3. Radisic, A., Oskam, G., and Searson, P. C., J. Electrochem. Soc., 151 (2004), C369-C374.CrossRefGoogle Scholar
4. Vereecken, P. M., Binstead, R. A., Deligianni, H., and Andricacos, P. C., IBM J. Res. Dev., 49 (2005), 318.CrossRefGoogle Scholar
5. Cao, Y., Taephaisitphongse, P., Chalupa, R., West, A. C., J. Electrochem. Soc., 148 (2001), C466-C472.CrossRefGoogle Scholar
6. Moffat, T. P., Wheeler, D., Kim, S.-K., and Josell, D., J. Electrochem. Soc., 153 (2006), C127–C132.CrossRefGoogle Scholar

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