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Carrier Pocket Engineering for the Design of Low Dimensional Thermoelectrics with High Z 3D T

Published online by Cambridge University Press:  01 February 2011

Takaaki Koga
Affiliation:
Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138
Stephen B. Cronin
Affiliation:
Department of Physics and Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139
Mildred S. Dresselhaus
Affiliation:
Department of Physics and Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139
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Abstract

The concept of carrier pocket engineering applied to Si/Ge superlattices is tested experimentally. A set of strain-symmetrized Si(20Å)/Ge(20Å) superlattice samples were grown by MBE and the Seebeck coefficient S, electrical conductivity σ, and Hall coefficient were measured in the temperature range between 4K and 400K for these samples. The experimental results are in good agreement with the carrier pocket engineering model for temperatures below 300K. The thermoelectric figure of merit for the entire superlattice, Z3DT, is estimated from the measured S and σ, and using an estimated value for the thermal conductivity of the superlattice. Based on the measurements of these homogeneously doped samples and on model calculations, including the detailed scattering mechanisms of the samples, projections are made for δ-doped and modulation-doped samples [(001) oriented Si(20Å)/Ge(20Å) superlattices] to yield Z 3D T ≈ 0.49 at 300K.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

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