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32nm Node Highly Reliable Cu/Low-k Integration Technology with CuMn Alloy Seed

Published online by Cambridge University Press:  10 August 2011

Shaoning Yao
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
Vincent McGahay
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
Matthew S. Angyal
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
Andrew H. Simon
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
Tom C. Lee
Affiliation:
IBM Microelectronics, Essex Junction, VT 05452
Cathryn Christiansen
Affiliation:
IBM Microelectronics, Essex Junction, VT 05452
Baozhen Li
Affiliation:
IBM Microelectronics, Essex Junction, VT 05452
Fen Chen
Affiliation:
IBM Microelectronics, Essex Junction, VT 05452
Paul S. McLaughlin
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
Oluwafemi O. Ogunsola
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
Stephan Grunow
Affiliation:
IBM Microelectronics, Hopewell Junction, NY 12533
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Abstract

This paper introduces a highly reliable Cu interconnect technology at the 32 nm node with CuMn alloy seed. A CuMn alloy liner seed process combined with a non-gouging liner has been integrated into the minimum-pitch wiring level. Stress migration fails with CuMn seed at plate-below-via structures were shut down by a non-gouging liner process. Integration with gouging liner and non-gouging liner is compared, and results of interaction with CuMn seed are discussed in this paper.

Type
Research Article
Copyright
Copyright © Materials Research Society 2011

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References

1. Christiansen, C., et al. ., “Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects”, IEEE Inter. Rel. Phys. Symp (IRPS) 2011.Google Scholar
2. Nogami, T., et al. ., “High reliability 32nm Cu/ULK BEOL based on PVD CuMn seed and its extendibility”, IEDM 2010, 33.5.133.5.Google Scholar
3. Edelstein, D., et al. ., “Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low- k BEOL,” in Proc. IEEE Int. Rel. Phys. Symp., 2004, pp. 316319.Google Scholar
4. Clevenger, L., et al. ., “Reliability challenges in copper metallizations arising with the PVD resputter liner engineering for 65 nmand beyond,” in Proc. IEEE Int. Rel. Phys. Symp., 2007, pp. 511515.Google Scholar
5. Yang, C.-C., et al. ., “Enhanced Via Integration Process for Copper/Ultralow-k Interconnects”, IEEE Electron Device Letters, Vol. 31, No. 4, 2010.CrossRefGoogle Scholar

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32nm Node Highly Reliable Cu/Low-k Integration Technology with CuMn Alloy Seed
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