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Issues in High-ĸ Gate Stack Interfaces

Published online by Cambridge University Press:  31 January 2011

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Abstract

We address current challenges in the fundamental understanding of physical and chemical processes that occur in the fabrication of the transistor gate stack structure. Critical areas include (1) the interface between bulk silicon and high-dielectric-constant (high-ĸ) insulators, (2) the interface between high-ĸ insulators and advanced gate electrodes, and (3) the internal interfaces that form within dielectric stacks with nonuniform material and structure compositions. We approach this topic from a fundamental understanding of bonding and electronic structure at the interfaces, and of film-growth kinetics in comparison with thermodynamics predictions. Implications for the dielectric/electrode interface with metallic gates and issues with integration will also be presented.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

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References

1.Lucovsky, G., J. Vac. Sci. Technol., A 19 (2001) p. 1353.CrossRefGoogle Scholar
2.Lucovsky, G., Rayner, G.B. Jr, Kang, D., Appel, G., Johnson, R.S., Zhang, Y., Sayers, D.E., Ade, H., and Whitten, J.L., Appl. Phys. Lett. 79 (2001) p. 1775.CrossRefGoogle Scholar
3.Johnson, R.S., Hong, J.G., and Lucovsky, G., J. Vac. Sci. Technol., B 19 (2001) p. 1606.CrossRefGoogle Scholar
4.Chambers, J.J., Busch, B.W., Schulte, W.H., Gustafsson, T., Garfunkel, E., Wang, S., Maher, D.M., Klein, T.M., and Parsons, G.N., “Effects of Surface Pretreatments on Interface Structure during Formation of Ultra-Thin Yttrium Silicate Dielectric Films on Silicon,” Appl. Surf. Sci. 181 (2001) p. 78.CrossRefGoogle Scholar
5.Chambers, J.J. and Parsons, G.N., J. Appl. Phys. 90 (2001) p. 918.CrossRefGoogle Scholar
6.De, I., Johri, D., Srivastava, A., and Osburn, C.M., Solid-State Electron. 44 (2000) p. 1077.CrossRefGoogle Scholar
7.Jiang, Q.-T., Faust, R., Lam, H., and Mucha, J., in Proc. IEEE 1999 Int. Interconnect Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 1999) p. 125.Google Scholar
8.Suh, Y.-S., Heuss, G.P., Zhong, H., and Misra, V., IEEE Symp. on VLSI Technology Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2001) p. 47.Google Scholar
9.Zhong, H., Hong, S.N., Suh, Y.-S., Lazar, H., Heuss, G., and Misra, V., in IEEE Int. Electron Devices Meet. Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2001) p. 467.Google Scholar
10.Lu, Q., Lin, R., Ranade, P., King, T.-J., and Hu, C., IEEE Symp. on VLSI Technology Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2001) p. 49.Google Scholar
11.Polishchuk, I., Ranade, P., King, T.-J., and Hu, C., IEEE Electron Device Lett. 22 (2001) p. 444.CrossRefGoogle Scholar
12. International Technology Roadmap for Semiconductors Home Page, http://public.itrs.net (accessed January 2002).Google Scholar