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New materials for post-Si computing: Ge and GeSn devices

Published online by Cambridge University Press:  14 August 2014

Suyog Gupta
Affiliation:
IBM T.J. Watson Research Center, USA; suyog@us.ibm.com
Xiao Gong
Affiliation:
Electrical and Computer Engineering, National University of Singapore, Singapore; elegong@nus.edu.sg
Rui Zhang
Affiliation:
Department of Information Science and Electronic Engineering, Zhejiang University, China; ruizhang@zju.edu.cn
Yee-Chia Yeo
Affiliation:
Electrical and Computer Engineering, National University of Singapore, Singapore; eleyeoyc@nus.edu.sg
Shinichi Takagi
Affiliation:
Department of Electrical Engineering and Information Systems, University of Tokyo, Japan; takagi@ee.t.u-tokyo.ac.jp
Krishna C. Saraswat
Affiliation:
Department of Electrical Engineering, Stanford University, USA; saraswat@stanford.edu
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Abstract

As Si-transistor technology advances beyond the 10 nm node, the device research community is increasingly looking into the possibility of replacing Si with novel, high mobility materials as the transistor channel. Among several possible candidate materials, germanium and germanium-tin alloys (GeSn) have emerged as strong contenders for the next generation of complementary metal oxide semiconductor (CMOS) transistors. This article presents a comprehensive overview of the state of the art in Ge and GeSn transistor research. We address several key material challenges involved in fabricating high-performance Ge/GeSn-based CMOS transistors, such as gate stack formation and achieving low-resistance contacts to transistor source/drain regions. Using Ge/GeSn as channel materials, we present a FinFET-based, Si-compatible CMOS solution for device dimensions expected in the 7 nm technology node, discuss the practical challenges involved in realizing this design, and highlight directions for future research.

Keywords

Type
Research Article
Copyright
Copyright © Materials Research Society 2014 

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