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Mitigating Curtaining Artifacts During Ga FIB TEM Lamella Preparation of a 14 nm FinFET Device

Published online by Cambridge University Press:  20 March 2017

Andrey Denisyuk ,
Tomáš Hrnčíř ,
Jozef Vincenc Oboňa ,
Sharang ,
Martin Petrenec  and
Jan Michalička
Andrey Denisyuk*
Affiliation:
TESCAN ORSAY HOLDING, Libušina třída 21, 62300 Brno, Czech Republic
Tomáš Hrnčíř
Affiliation:
TESCAN Brno, Libušina třída 1, 62300 Brno, Czech Republic
Jozef Vincenc Oboňa
Affiliation:
TESCAN ORSAY HOLDING, Libušina třída 21, 62300 Brno, Czech Republic
Sharang
Affiliation:
TESCAN Brno, Libušina třída 1, 62300 Brno, Czech Republic
Martin Petrenec
Affiliation:
TESCAN Brno, Libušina třída 1, 62300 Brno, Czech Republic
Jan Michalička
Affiliation:
TESCAN ORSAY HOLDING, Libušina třída 21, 62300 Brno, Czech Republic
*
*Corresponding author. andrey.denisyuk@tescan.cz
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Abstract

We report on the mitigation of curtaining artifacts during transmission electron microscopy (TEM) lamella preparation by means of a modified ion beam milling approach, which involves altering the incident angle of the Ga ions by rocking of the sample on a special stage. We applied this technique to TEM sample preparation of a state-of-the-art integrated circuit based on a 14-nm technology node. Site-specific lamellae with a thickness <15 nm were prepared by top-down Ga focused ion beam polishing through upper metal contacts. The lamellae were analyzed by means of high-resolution TEM, which showed a clear transistor structure and confirmed minimal curtaining artifacts. The results are compared with a standard inverted thinning preparation technique.

Keywords

TEM samplelamellaintegrated circuitFinFET device
Type
Materials Science Applications
Information
Microscopy and Microanalysis , Volume 23 , Issue 3 , June 2017 , pp. 484 - 490
Copyright
© Microscopy Society of America 2017 

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