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RF CMOS power amplifier using a split inter-stage inductor for IEEE 802.11n applications

Published online by Cambridge University Press:  15 August 2016

Minoh Son
Affiliation:
School of Electronic Engineering, College of Information Technology, Soongsil University, 369 Sangdo-Ro, Dongjak-Gu, Seoul, 06978, Republic of Korea. Phone: +82-2-828-7166
Jinho Yoo
Affiliation:
School of Electronic Engineering, College of Information Technology, Soongsil University, 369 Sangdo-Ro, Dongjak-Gu, Seoul, 06978, Republic of Korea. Phone: +82-2-828-7166
Inseong Kang
Affiliation:
School of Electronic Engineering, College of Information Technology, Soongsil University, 369 Sangdo-Ro, Dongjak-Gu, Seoul, 06978, Republic of Korea. Phone: +82-2-828-7166
Changhyun Lee
Affiliation:
School of Electronic Engineering, College of Information Technology, Soongsil University, 369 Sangdo-Ro, Dongjak-Gu, Seoul, 06978, Republic of Korea. Phone: +82-2-828-7166
Jihoon Kim
Affiliation:
Chip Development Team, GigaLane Co., Ltd., 46, Samsung 1-Ro 5Gil, Hwaseong-Si, Gyeonggi-Do, Republic of Korea
Ho Jong Park
Affiliation:
Chip Development Team, GigaLane Co., Ltd., 46, Samsung 1-Ro 5Gil, Hwaseong-Si, Gyeonggi-Do, Republic of Korea
Young-Bae Park
Affiliation:
Chip Development Team, GigaLane Co., Ltd., 46, Samsung 1-Ro 5Gil, Hwaseong-Si, Gyeonggi-Do, Republic of Korea
Changkun Park
Affiliation:
School of Electronic Engineering, College of Information Technology, Soongsil University, 369 Sangdo-Ro, Dongjak-Gu, Seoul, 06978, Republic of Korea. Phone: +82-2-828-7166
Corresponding
E-mail address:

Abstract

In this study, we design a differential CMOS power amplifier using a 180-nm SOI RFCMOS process for 802.11n (64-QAM, 20 MHz bandwidth, 9.6 dB peak to average power ratio (PAPR)) applications. To minimize the chip area and mismatch in differential signals, we propose a layout method with an inter-stage matching network using a split inductor. By virtue of the symmetrical layout of the proposed split inductor, the mismatch in the differential signals is minimized, while the interconnection lines between the driver and power stages are shortened to minimize the overall chip area and the loss induced by the resistive parasitic components. The designed power amplifier is measured using a wireless local area network (WLAN) 802.11n signal to verify the feasibility of the proposed layout technique. The power amplifier achieved 20.34 dBm output power, while the measured EVM for the 802.11n applications is satisfied. From the measured results, we successfully prove the feasibility of the proposed power amplifier.

Type
Research Papers
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2016 

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References

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