So far, we have described the structures and the principles of operation of field effect transistors, and how such principles and features need to be considered in the context of developing a compact model of the device for use in a circuit simulator to aid power amplifier design. We have also described in some detail how to characterize and model the transistor package and its internal passive components, in the electromagnetic, electrical, and thermal environments that surround the transistor. We shall now begin to focus our attention on the transistor itself: the active semiconductor channel where the transistor action takes place, and the gate, source, and drain electrodes that enable electrical connection to the rest of the power transistor's environment.
A typical high-power discrete LDMOS transistor die is shown in Fig. 6.1. The manifolds for the gate and drain, where the bondwires connect to the rest of the circuit, can be seen clearly. The manifolds also feed the many gate and drain fingers that form an inter-digitated pattern on the silicon surface, defining the individual transistor units that form the whole device. The source connection is made through the silicon itself to the back side of the die, making contact directly to the package, which provides the electrical ground and also a thermal reference: it is easy to make a repeatable temperature measurement at the package when operating the transistor under test.