Ferroelectric random access memory (FeRAM) is believed to be the most promising candidate for the next generation non-volatile memory due to its fast access time and low power consumption. Fabrication technologies of FeRAM can be divided into two parts: CMOS technologies for circuits which are standard and can be shared with traditional IC process line, and process relating to ferroelectric which is separated with CMOS process and defined as backend module. This paper described technologies for integrating ferroelectric capacitors into standard CMOS, mainly about modeling of ferroelectric capacitors and backend fabrication technologies. Hysteresis loop of the ferroelectric capacitor is the basis for FeRAM to store data. Models to describe this characteristic are the key for the design of FeRAM. A transient behavioral ferroelectric capacitor model based on C-V relation for circuit simulation is developed. The arc tangent function is used to describe the hysteresis loop. “Negative capacitance” phenomenon at reversing points of applied voltage is analyzed and introduced to the model to describe transient behaviors of the capacitor. Compact equivalent circuits are introduced to integrate this model into HSPICE for circuit simulation. Ferroelectric materials fabrication, electrodes integration and etching are the main technologies of FeRAM fabrication process. An metal organic chemical vapor deposition (MOCVD) process is developed to fabricate high quality Pb(Zr1-xTix)O3 (PZT) films. Pt is known to cause the fatigue problems when used as electrodes with PZT. Ir is used as electrodes to improve the fatigue property of PZT based capacitors, and mechanism of the fatigue is analyzed. Hard mask is used to reduce the size of the capacitors and damage caused in etching process. In our process, Al2O3 is developed as hard mask, which simplifies the FeRAM backend integration process.