Digitally-assisted analog and analog-assisted digital techniques are increasingly needed in future circuit and system designs, as FinFET and FDSOI replace planar CMOS technology at advanced process nodes of 20 nm and beyond. The intrinsic features of these new devices are lowering the barrier between the analog and the digital worlds, allowing unprecedented performance to be achieved by assisting digital circuits with analog techniques or analog circuits with digital techniques.
As CMOS technologies scale to smaller nodes, digital designs enjoy obvious benefits in terms of higher speed and lower power consumption. However, scaling doesn't happen so readily or cleanly with analog designs. Analog circuits frequently make use of “digital assistance”, which allows simplification of the critical analog circuits that don't scale easily. Digitally-assisted analog techniques, such as calibration, allow for considerable relaxation of the analog performance, which can be used for minimizing both area and power consumption. Another trend is the transition of traditional analog functions to the digital domain. Compared to their analog mixed-signal counterparts, all-digital implementations are scalable, insensitive to noise, and robust against process variations. On the other hand, driven by the worldwide demand for low-power application processors, dynamic voltage/frequency scaling (DVFS) and adaptive voltage scaling (AVS) are typically used to reduce energy consumption in mobile systems. DVFS and AVS are enabled for optimal power management by analog techniques that monitor the on-die process, voltage and temperature variations.
The objective of this book is to discuss practical design considerations in high-performance scaled CMOS processes, established circuit techniques that take advantage of scaled CMOS process technology in analog, digital, RF, and system-on-chip (SoC) designs, and the outlook for the future in the context of challenges and solutions.
The book consists of nine chapters. Chapter 1 overviews the history of transistor scaling in recent 20 years. Several traditional scaling implications like short-channel effects, followed by the ever-increasing impacts of process variation and parasitic elements are revisited. This chapter also introduces several design issues specific to the recent nano-scale transistors, which include well proximity, shallow trench isolation (STI) stress-induced performance variation, aging effects, and so on.
Chapter 2 presents FinFETs from devices to architectures. It surveys different types of FinFETs, various FinFET asymmetries and their impact, and novel logic-level and architecture-level trade-offs. It also reviews analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.