Heterojunction with intrinsic thin layer (HIT) solar cells have achieved conversion efficiencies higher than 22%. Yet, many questions concerning the device physics governing these cells remain unanswered. We use numerical modeling to analyze the role of a-Si:H layers and tunneling on cell performance. For cells with n-type c-Si (n-HIT cells), incorporating the indium-tin-oxide (ITO) as an n-type semiconductor creates an n
+/p/n structure. Most device simulations do not work with this structure. Our modeling indicates that the n
+/p/n device often produces irregular S-shaped current density–voltage (J-V) curves, which have been observed experimentally but were not previously understood. However, if tunneling is included, there are specific conditions where the n
+/p/n structure performs as a robust solar cell with efficiencies exceeding 20%. Additional analysis examines voltage-dependent carrier collection in n-HIT cells, as well as material and interface properties that limit fill factor.
In p-HIT cells, modeling the ITO layer as a semiconductor, rather than as a metallic contact, significantly reduces the impact of a-Si:H layer parameters on device performance. In p-HIT cells, the a-Si:H layers adjacent to the ITO layer play the role of a buffer that reduces interface recombination at the a-Si:H/c-Si interface and prevents tunneling of electrons from the ITO layer to the c-Si absorber. Tunneling through the a-Si:H layers adjacent to the back contact is important to attain regular J-V curves.