The effects of iron contamination on gate oxide characteristics are examined from an experimental and modeling perspective. Gate oxide integrity is measured for silicon wafers contaminated with 1010 to 1014cm−3 of iron. Thermal oxides of 8, 10,13 and 20nm are studied. Iron concentration in silicon is measured non-destructively using Surface Photovoltage (SPV) minority carrier lifetime analysis. The SPV analysis technique is described. Based on the experimental data, allowable threshold iron contamination levels for various gate oxide thicknesses are established. For 10nm oxides, iron concentration cannot exceed 8×1010cm−3 without severe degradation in oxide quality. The threshold contamination level for 20nm oxides is 200 times higher. Time dependent dielectric breakdown (TDDB) test results indicate detrimental reliability effects can occur at even lower contamination levels.