A procedure for preparing cross-section samples of specific regions on an integrated circuit die is outlined. The procedure involves the use of glass slabs to prepare the sample stack used for cross-sectioning. The transparent glass slabs on the top surface of the die enable monitoring of the region of interest during the thinning process. This ensures that the region of interest will be located in the electron-transparent section used for TEM imaging. Samples prepared using this technique are sturdy enough to survive successive thinning and observation in a TEM. The glass slides do not give any charging problems and generally thin much slower than the silicon so as to provide added stability to the sample. An additional advantage is that the sample thickness can be accurately measured using the vernier attachment on an optical microscope during the sample thinning process. The imaging of specific NMOS transistors fabricated on buried oxide layers is illustrated.