The metal gate high k interaction is one of the dominant processes influencing the electrical performance (Vt, charge accumulation,..) of advanced gate stacks. These interactions are influenced by the entire thermal budget and the presence of reactive elements (on top/ within the material gate) such that relevant measurements can only be performed after a full processing cycle and on a complete gate stack.

In such cases the relevant metal gate high k interface is a buried interface located below the metal gate (+ Si cap) and is not accessible for standard characterization methods like x-ray photoemission spectroscopy (XPS) due the limited escape depth of the photoelectrons. Moreover the presence of a conductive metal gate prevents the application of techniques such as conductive atomic force microscopy (C-AFM), to probe the local distribution of the defects, trapping sites and local degradation upon stressing. XPS in combination with layer removal steps like ion beam sputtering will destroy the bonding information and is thus not applicable. Chemical etching of the metal gate stack prior to the XPS measurements requires an extremely precious control of the etching in order to stop 1-2 nm before the high k metal interface.

As an alternative we have developed a backside removal approach, that allows us to investigate using techniques such as XPS and C-AFM, the metal gate high k interface.

Maintaining or improving device performance while scaling semiconductor devices, necessitates the development of extremely shallow (< 20 nm) source/drain extensions with a very high dopant concentration and electrical activation level. Whereas solutions based on RTA with cocktail implants have been proposed in previous generations, sub-45 nm technologies will require even shallower junctions which motivates the research effort on milli-second anneal approaches as these hold the promise of minimal diffusion coupled with high activation levels [1]. Laser annealing is one of these concepts proposed to achieve the junction specifications and is typically described as a msec anneal process. Different from lamp based concepts which illuminate a full wafer simultaneously, the laser has an illuminated area which is much smaller than the wafer size thus necessitating a dedicated scanning pattern. In such a case one is potentially faced with areas subject to multiple overlaps and/or different temperatures and thus issues related to within wafer and within die uniformity need to be addressed.

In this work we use optimized metrology to probe such macro- and micro non-uniformity and determine the origin of the various components contributing to the observed non-uniformity patterns (laser stitching patterns, laser beam uniformity, optical path) and their impact on the local sheet resistance.

The electrical performance of junctions in SiGe Strain Relaxed Buffers (SRB's) with a strained Si top layer is investigated. Most of the SRB's grown in this experiment use a thin C-doped SiGe layer, which allows to fabricate thin (∼250nm) SRB's with a high relaxation degree. The effects of Threading Dislocation Density (TDD) and C-rich layer depth on the electrical behaviour of n+/p and p+/n junctions are studied. The C atoms in the junction's Space Charge Region (SCR) give rise to defects and induce a noticeable increase in the leakage. The effect of the TDD on the leakage in n+/p junctions is linear over the complete voltage range applied, while for p+/n junctions, only a small effect on leakage is measured at V=1V reverse for TDD's below 1×107cm-2. For low reverse voltages, the current varies more linearly with TDD.

We study the existence of closed characteristics on three-dimensional energy manifolds of second-order Lagrangian systems. These manifolds are always non-compact, connected and not necessarily of contact type. Using the specific geometry of these manifolds, we prove that the number of closed characteristics on a prescribed energy manifold is bounded below by its second Betti number, which is easily computable from the Lagrangian.

Solid phase epitaxial regrowth (SPER) has been proven to be highly advantageous for ultra shallow junction formation in advanced technologies. Application of SPER to strained Si/SiGe structures raises the concern that the Ge may out diffuse during the implantation and/or anneal steps and thus reduce the strain in the top silicon layer.

In the present studies we expose 8-30 nm strained silicon layers grown on thin relaxed SiGe-buffers, to implant conditions and anneal cycles, characteristic for formation of the junctions by solid phase epitaxial regrowth and conventional spike activation. The resulting Geredistribution is measured using SIMS. Based on the outdiffused Ge-profiles the Ge-diffusion coefficient has been determined in the temperature range of 800-1100C from which an activation energy of ∼ 3.6 eV can be deduced. Up to 1050 C, 10 min, even a 30 nm strained film remains highly stable and shows only very moderate outdiffusion.

We also have observed a far more efficient, athermal Ge-redistribution process linked to the implantation step itself. This was studied by analysing the Ge-redistribution following an Asimplant (2-15 keV, 5 1014 – 3 1015 at/cm2). It is shown that the energy of the implant species (or more specifically the position of the damage distribution function relative to the Ge-edge) plays a determining factor with respect to the Ge-migration. For implants whereby the damage distribution overlaps with the Ge-edge, a very efficient transport of the Ge is observed, even prior to any anneal cycle. The migration is entirely correlated with the collision cascade and the resulting (forward!) Ge-recoil distribution. The scaling with dose for a given energy links the observed Ge-profile with a broadening mechanism related to the number of atom displacements induced in the sample within the vicinity of the Si-SiGe-transition.

In advanced CMOS technology nodes one may achieve further enhancement of device performance by carrier mobility modification in the transistor channel. The carrier mobility enhancement can be realized by formation of strained silicon layers on a Si1−xGex strain relaxed buffer. Formation of source and drain extensions on such structures need to satisfy one additional requirement, the formation process, including the activation related thermal budget should not relax the strain in the channel. In this paper we separately investigate the role of amorphization during implantation, different doping impurities and thermal budget on the junction and the transistor channel regions properties. Two approaches of dopant activation are discussed: low temperature solid phase epitaxial regrowth and high temperature conventional spike.

Tensile strained Si on SiGe Strain Relaxed Buffers (SRB) is an interesting candidate to increase both electron and hole mobility which results in improved device performance. Most of this work was/is based on thick (several μm), step-graded SRBs with or without Chemical Mechanical Polishing (CMP) planarisation. This approach bears several disadvantages such as issues with STI formation in the thick SiGe structure, and considerable self-heating effects due to the lower thermal conductivity of the SiGe material. Further, pMOS improvement requires SRBs with high Ge contents (> 30 %), which complicates device fabrication even more. To overcome these issues, we developed a new and cost efficient type of thin SRB (∼200 nm). The concept is based on the introduction of a thin carbon-containing layer during growth of a constant composition SiGe layer. The process relies on standard Chemical Vapor Deposition epitaxial technology without need for CMP. It is designed to allow both non-selective growth on blanket wafers and selective growth in the active area of structured wafers with Shallow Trench Isolation (STI). The selective epitaxial process for strained Si on thin SRBs proposed here, allows relatively simple and cost-effective fabrication of strained Si layers on existing STI structures without any process modification. Further, it offers a very flexible fabrication scheme to independently improve nMOS and pMOS devices. The SRB quality is comparable to the best reported in literature so far, with 70 % and 53 % mobility enhancements for long channel nMOSFETs on 22 % Ge SRBs grown on blanket and STI patterned wafers, respectively.

Junctions were formed in thin SiGe/strained Si substrates with a thickness of 250-350 nm to assess the effect of different buffer layer parameters (bandgap, dislocations, thickness) on the junction leakage density that can be expected in MOSFET devices. The implantations used are standard well, channel and Highly Doped Drain (HDD) implants. Both p+/n and n+/p junctions were evaluated. The total thickness of the buffer layers was varied to compare the effect of different structural layers on the diode leakage. This investigation shows that the effect of an increased defect density is dominant at room temperature for the strained Si samples, resulting in 4-5 orders of magnitude increase in leakage. However, there is a different gradation in leakage dependence for thick and thin buffer layers, especially at higher temperatures.

In the path to the introduction of high-k dielectric into IC components, a large number of challenges have still to be solved. Some of the major issues concern the low mobility of carriers and the reliability of the devices. Trapped charges in the stack have been identified as being the cause of these issues. With this in mind, we used Conducting Atomic Force Microscopy, combined with physical analysis to understand the nature of these charges. In this contribution, we have studied the uniformity of thin HfO2 layers, with and without anneal. The Conducting Atomic Force microscopy measurements show spots of higher conductivity. Recording local IV's in those ‘weak’ spots suggests that they consist of positive charge. On the other hand, XPS and ToFSIMS analysis show a diffusion of the interfacial SiO2 upwards into the high-k layer. Finally, the comparison of samples with differing high-k material and crystallinity indicates a strong correlation between the weak spots and the presence of silicon in the film.

In the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture.

In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (<1nm/dec) with leakage suitable for low power applications, while the flash anneal has the benefit of higher solid solubility (>4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Thermal stability of amorphous phases in various high-k layers (Al2O3, ZrO2, HfO2, ZrAlOx, HfAlOx and HfSiOx) and the phase transformation of crystalline ZrO2 and HfO2 were studied experimentally, as functions of surface preparation, deposition conditions, material composition and post deposition thermal treatment. It is found that pure ZrO2 and HfO2 show relatively low crystallization onset temperatures. The crystalline ZrO2 or HfO2 phases are tetragonal or monoclinic, depending on the layer thickness. The phase transformation of metastable t-phase into stable m-phase has been observed in ZrO2 and HfO2. Crystallization behavior of Al2O3 depends on the surface preparation of the substrate. ALCVD grown Al2O3 layers on an oxide-based surface remain amorphous after 1100°C spike annealing, while those on HF-last surface crystallize at temperatures around 800°C. Alloying Al2O3 into ZrO2 and HfO2 can improve their resistance to crystallization under thermal exposure. The kinetics of the crystallization in the alloys can be described by linear TTT curves. Hf-aluminates show better thermal stability than Zr-aluminates. A defect model relative to the phase transformation is discussed, based on the above observations.

Targeting very thin equivalent oxides (<1 nm) requires the deposition of (very) thin dielectrica onto silicon surfaces with minimal interfacial oxide. Typically, high-k dielectric layers are deposited using ALD or MOCVD with, at present, a prime emphasis on Hf-based high-k dielectrics, either as pure HfO2, as silicate or mixed with Al2O3. In some cases nitrogen is added to improve the high-temperature stability. Depending on the deposition conditions ALD as well as MOCVD show serious deficiencies in terms of film closure and material density for ultra thin (<3 nm) films. Various surface preparation methods and deposition conditions are used to improve the film quality. Detailed studies on the film growth and its evolution requires the use of many analytical methods such as Rutherford Backscattering Spectrometry, Low Energy Ion Scattering, Time-of-flight SIMS, (spectroscopic) ellipsometry and X-ray photoelectron spectroscopy. When trying to correlate the results in terms of film thickness, apparent discrepancies can be observed which relate to non-homogeneous growth and reduced material density.

A fast screening technique is used to study the ALD HfO2 growth behavior on different types of starting surfaces (H-passivated, chemical oxide, thermal oxide). The amount of Hf deposited at the early stages of the ALD process is measured by means of RBS. The HfO2 film quality on different starting surfaces is examined with ToFSIMS. The results suggest an island growth mechanism on a H-terminated starting surface: nucleation, development of separated nuclei and flattening. It is shown that ALD growth starts faster if –OH groups are present on the surface. A remote H2 plasma surface pre-treatment at room temperature is also studied. The influence of the plasma exposure time and number of water pulses prior to HfO2 deposition was examined. The H2 plasma surface pre-treatment can be considered as a promising candidate for sub 1 nm EOT performance.

This paper discusses metal organic chemical vapor deposited (MOCVD) HfO2 layers using tetrakis(diethylamido)hafnium (TDEAH) as precursor. We have studied the influence of the starting surface and deposition temperature on the growth kinetics and physical properties of the HfO2 layers. Important characteristics such as crystalline state, density, and organic contamination in the layers were found to be dependent on these parameters.

Typical for this deposition process is the formation of an interfacial layer underneath the high-k layer. Its composition and thickness, affecting scaling of the equivalent oxide thickness, are shown to be closely related to the HfO2 process parameters mentioned above.

Finally, we will show electrical results for HfO2/polySi gate stacks indicating the effect for deposition temperature.

Carrier Illumination™ (CI) is an optical technique for non-destructive in-line monitoring of post-anneal junction depth and pre-anneal PAI depth and dose with wafer mapping capabilities. This work intends to extend the use of the CI-measurements from a range-specific quantitative measurement towards a more universal quantitative analysis of junction depth, profile abruptness and implant dose. For that purpose this paper presents a systematic study of the CI response to a wide variety of post anneal implant processes, varying parameters including implant species, dose and energy, annealing condition, and surface preparation.

Samples containing B, BF2 and As-implants with and without Ge PAI layers, with junction depths between 10-120 nm, were measured. In addition near-ideal box-like profiles (as obtained with CVD-growth) were fabricated and measured. For the abrupt CVD profiles, CI measures the junction position with sub-nm resolution independent of the CI-analysis conditions. For more graded profiles resulting from annealed implants, the correlation to the SIMS junction depth becomes a function of generation laser current (which is proportional to the applied power). As the concentration level, at which the correlation is made, can be adjusted over a concentration range of approximately 2x1018 to 2x1019/cm3 by changing the laser current, a route towards correlating the CI measurement with profile abruptness becomes feasible.

Continued device scaling requires the formation of ever-shallower junctions with low resistance. A desirable option to form these junctions is still the use of conventional ion implantation. However in order to meet the junction depth/sheet resistance goals, a strong reduction in implant energy and increase in implant dose is required. Earlier work for B and BF2-implants, has suggested that during low energy ion implantation self-sputtering may become an important factor influencing/limiting the retained dose. The basic mechanism for the selfsputtering with increasing dose is the increasing dopant concentration at the surface leading to an increased probability for re-emission by the sputtering process. Simple models describing ion retention in combination with sputtering are based on this concept and indeed predict a selfsputtering process limiting the final retained dose. Unfortunately the theoretical calculations only predict a significant sputtering at doses >51016 at/cm2 whereas experimental results already show a limit in retained dose at 5 1015at/cm2.

In order to confirm the experimental data, low energy B, BF2, As and Sb implants have been made. Dose retention was monitored using nuclear reaction analysis and RBS whereby details of the dopant profile (redistribution) were studied using high resolution SIMS. For As and Sb no self-sputtering up to a dose of 1 1016at/cm2 can be found. For B a small dose loss (<10%) is seen significantly below the literature data. For BF2 a 20 % dose loss is observed. None of the SIMS profiles provide sufficient evidence for enhanced B-surface migration as required to explain the enhanced self-sputtering. On the other hand such a surface migration is reminiscent of the observations in SIMS whereby also an enhanced mobility of B during ion irradiation is required to explain the anomalous B-surface peak in many SIMS profiles. Based on the SIMS profiles a component sputter yield for B can be derived which is significantly higher than the matrix sputter yield suggesting a weak bonding of the segregated species leading to a reduced surface binding energy and thus enhanced sputtering yield.

Initial studies (using Scanning Spreading Resistance Microscopy) on the lateral diffusion of B and As have shown an important influence of the thickness of oxy/nitride spacers. The latter phenomenon was tentatively ascribed to stress enhanced diffusion under the spacer region [1]. These studies have been complemented with Scanning Capacitance Microscopy (SCM) measurements, which confirm the SSRM-data. In fact both techniques shows a similar increase in lateral diffusion with increasing spacer thickness (∼ 0.2 nm/nm spacer thickness), whereby no effect is observed on the vertical diffusion. When using spacers with or without TEOS-liner, fairly similar enhancements could be seen. Micro-Raman and CBED stress measurements for these cases do however show a large reduction in stress when a TEOS-liner is used, suggesting that the correlation (at least to the final) stress is not really justified. A possible explanation could however be that the lateral diffusion occurs before the stress relaxation within the thermal treatment. In order to elucidate the diffusion mechanism (initial stress, interstitials, hydrogen incorporation, TED,..) we have expandedthe experimental matrix with a vacancy diffuser such as Sb and simulated the potential H-incorporation duringthe nitride deposition by a hydrogen anneal. Moreover we also have studied the impact of TED by splits with RTP-anneals before the nitride deposition.

State-of-the-art semiconductor devices require an accurate control of the complete twodimensional dopant distribution. The routine use of process simulators to predict the envisaged distributions and their resulting accuracy, is strongly linked to the physical models contained in these programs as well as their calibration. Whereas SIMS and SRP have been used extensively for the calibration of 1D-profiles, calibration of 2D-profiles has been very limited.

In this work, we report some results obtained with the 2D-profiling techniques SSRM (Scanning Spreading Resistance Microscopy) and SCM (Scanning Capacitance Microscopy ) for the study of two-dimensional effects on diffusion. In particular, we discuss the role of the nitride spacer on the lateral diffusion of arsenic and boron. Using series of transistors with different nitride spacers with or without TEOS-liners, a strong dependence between the lateral diffusion and the nitride spacer thickness can be observed using SSRM and SCM. The process flow eliminates the possible contribution of Transient enhanced diffusion (TED) as a dominant mechanism. At the same time an enhancement of the lateral stress underneath the spacers has been observed with CBED and Raman, suggesting a correlation between the lateral diffusion and the nitride spacers. The enhanced diffusion of As and B is strongly linked to the spacer size whereby the differences in enhancement suggest that the proximity of the dopants to the stress field field region is an important parameter.

We have studied CoSi2 formation in the presence of a Cr or Mo interlayer or capping layer. We shall show that, contrary to what was previously reported, Cr and Mo may be used as interlayers to grow epitaxial CoSi2. However, unlike for Ti, the thickness of the interlayer is very important. If the Cr or Mo interlayer is too thick (> 5 nm), polycrystalline CrSi2 or MoSi2 are formed first and epitaxial growth of CoSi2 becomes impossible. However, both XRD and random/channeling RBS results indicate that for a 2-3 nm interlayer of Cr or Mo, CoSi2 forms epitaxially on Si(100). For thinner interlayers, there is a preferential (220) and (400) orientation. This can be explained by the presence of Cr or Mo on the CoSi grain boundaries, which will affect the heterogeneous nucleation of CoSi2.