The use of millisecond annealing to meet ultra-shallow junction requirements for sub-45nm CMOS technologies is imperative. In this study, the effect of flash anneal parameters is presented. Reduced dopant diffusion and lower sheet resistance Rs is achieved for intermediate temperature T
int = 700°C (vs. 800°C). Significantly lower Rs is achieved with peak temperature Tpeak = 1300°C (vs. 1250°C). Multiple shots provide for lower Rs, albeit at the expense of increased dopant diffusion. Based on a simple quantitative model, an optimal flash anneal can achieve 82% dopant activation efficiency.