SrBi2Ta2O9(SBT) capacitors were integrated to the structure for a mega-bit nonvolatile memory, and their electrical properties after metallization were investigated. Annealing above 500°C after contact-etching was necessary to obtain good electrical properties. A well saturated hysteresis loop with 2Pr of more than 15μC/cm2 was obtained for the 0.7×0.7μm capacitor. The read-out polarization was very stable in 105 sec after the write-pulse. No fatigue or imprint was observed up to 1011 cycles. These results show suitability of SBT capacitors for a mega-bit non-volatile memory.

Phosphorus-doped polycrystalline silicon used to plug the high-aspect-ratio, deep-submicron contact-holes connecting suicide metallization layers and substrate diffusion or silicide/polycide layers used in prototype 64 and 256 mega-bit DRAM devices acts as a dopant source at the silicidc/plug and plug/substrate interfaces during thermal processing. This outdiffusion of phosphorus from the contact-hole plug can lead to increased contact resistance which degrades device reliability and performance. Non-doped silicon, titanium, and titanium nitride films have been investigated as phosphorus outdiffusion buffer or barrier layers which reduce or prevent interaction between the doped contact-hole plug and surrounding conduction layers. Non-doped silicon diffusion buffer layers alternately deposited with in situ-doped silicon dopant source layers have been found to be effective in reducing outdiffusion into the substrate whereas a TiN diffusion barrier layer sputter deposited between the plug and WSix metallization prevents dopant outdiffusion into the WSix layer.

The surface morphology of SOI has been studied. The surface is very wavy and contains protrusions. Crystal orientations for SOI without protrusions were close to (100), while those for SOI with protrusions were close to either (111) or (101). The angle of orientation rotation for SOI without protrusions was less than 5 degrees over a 600um long SOI stripe, while the angle of SOI with protrusions was about 30 degrees. Threshold voltages of pMOSFET with protrusions in the channel were generally larger than those without protrusions in the channel.