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The critical adhesion energy of benzocyclobutene (BCB)-bonded wafers is
quantitatively investigated with focus on BCB thickness, material stack and
thermal cycling. The critical adhesion energy depends linearly on BCB
thickness, increasing from 19 J/m2 to 31 J/m2 as the
BCB thickness increases from 0.4 μm to 2.6 μm, when bonding silicon wafers
coated with plasma enhanced chemical vapor deposited (PECVD) silicon dioxide
(SiO2). In thermal cycling performed with 350 and 400 oC peak temperatures,
the significant increase in critical adhesion energy at the interface
between BCB and PECVD SiO2 during the first thermal cycle is
attributed to relaxation of residual stress in the PECVD SiO2
layer. On the other hand, the critical adhesion energy at the interface
between BCB and PECVD silicon nitride (SiNx) decreases due to the
increase of residual stress in the PECVD SiNx layer during the
first thermal cycle.
Wafer-level three-dimensional (3D) integration as an emerging architecture
for future chips offers high interconnect performance by reducing delays of
global interconnects and high functionality with heterogeneous integration
of materials, devices, and signals. Various 3D technology platforms have
been investigated, with different combinations of alternative alignment,
bonding, thinning and inter-wafer interconnection technologies. Precise
alignment on the wafer level is one of the key challenges affecting the
performance of the 3D interconnects. After a brief overview of the
wafer-level 3D technology platforms, this paper focuses on waferto-wafer
alignment fundamentals. Various alignment methods are reviewed. A higher
emphasis lies on the analysis of the alignment accuracy. In addition to the
alignment accuracy achieved prior to bonding, the impacts of wafer bonding
and subsequent wafer thinning will be discussed.
Monolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.
The growth morphology of Ag on GaAs (110) surfaces, at low coverages, is investigated with Monte Carlo simulations using a solid-on-solid model. Experimentally Ag deposited at room temperature forms 3D isotropic islands and forms needle-like islands elongated along the <110> direction when deposited at 250°C. Preliminary simulation results using 2D island growth model indicated that the elongation of islands at 250°C deposition is due to anisotropic surface diffusion and nearest-neighbor interactions along the <100> and <110> directions. The island morphologies obtained using a 3D island growth model are in good agreement with experimentally observed morphologies.
Computer simulations are used to study ionized physical vapor deposition, with ionized magnetron sputtering of copper as the primary system of interest. The effects of sputtering-ion energy and sputtering-ion angular flux distributions on the evolution of sub-micron scale features during IPVD are explored using the EVOLVE simulator. Our goal is to develop semi- quantitative engineering relationships that accurately predict the trends in experimental responses to changes in operating conditions. A sticking- factor model is used to describe deposition by neutrals. The sticking-factor of incident Cu atoms can depend on arrival angle and energy. Copper ions can also become part of the growing film. Energy and angular dependent sputter yields for both copper and argon ions are taken alternately from MD simulation results and a semi-empirical model. Sputtered material is ejected from the surface, tracked through the gas phase, and allowed to redeposit. Redeposition is also modeled via a sticking-factor based approach. The redistribution of film material results in non-intuitive profiles and complex relationships between final profiles and process parameters such as sample bias and neutral-to-ion flux ratios.
Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.
A three-step baseline process for thinning of bonded wafers for applications in threedimensional (3D) integration is presented. The Si substrate of top bonded wafer is uniformly thinned to ~35 μm by backside grinding and polishing, followed by wet-etching using TMAH. No visible changes at the bonding interface and damage-free interconnect structures are observed after the thinning process. Both mechanical and electrical integrity of the bonded pairs are maintained after the three-step baseline thinning process, with electrical tests on wafers with multi-level copper interconnect test structures showing only a slight change after bonding and thinning. This thinning process works well for Si removal to an etch-stop layer, although present process uniformity is not adequate to thin bulk Si substrates. Other issues such as wafer breakage and edge chipping during Si thinning and their possible solutions are also addressed.
A process to bond 200 mm wafers for wafer-level three-dimensional integrated circuit (3D-IC) applications is discussed. Four-point bending is used to quantify the bonding strength and identify the weak interface. Using benzocylcobutene (BCB) glue, the bonding strength depends on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). A seamless BCB-to-BCB bond interface provides the highest bonding strength compared to other interfaces in these structures (> 34 J/m2). Mechanical and electrical properties of a wafer with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding process for 3D ICs.
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