Maintaining or improving device performance while scaling semiconductor devices, necessitates the development of extremely shallow (< 20 nm) source/drain extensions with a very high dopant concentration and electrical activation level. Whereas solutions based on RTA with cocktail implants have been proposed in previous generations, sub-45 nm technologies will require even shallower junctions which motivates the research effort on milli-second anneal approaches as these hold the promise of minimal diffusion coupled with high activation levels . Laser annealing is one of these concepts proposed to achieve the junction specifications and is typically described as a msec anneal process. Different from lamp based concepts which illuminate a full wafer simultaneously, the laser has an illuminated area which is much smaller than the wafer size thus necessitating a dedicated scanning pattern. In such a case one is potentially faced with areas subject to multiple overlaps and/or different temperatures and thus issues related to within wafer and within die uniformity need to be addressed.
In this work we use optimized metrology to probe such macro- and micro non-uniformity and determine the origin of the various components contributing to the observed non-uniformity patterns (laser stitching patterns, laser beam uniformity, optical path) and their impact on the local sheet resistance.