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The impact of device processing and plasma treatments at different plasma conditions on the electronic transport properties of GaN/AlGaN/GaN heterostructures was investigated as well as annealing in nitrogen atmosphere at 425°C. The electrical properties are characterized by Hall-effect measurements while electron spectroscopy and X-ray measurements are used to investigate changes in the surface chemical composition and in the layer structure, respectively. It is demonstrated that these layer structures are quite sensitive even to non-plasma based processing. Furthermore, treatments in SF6 and N2 based plasmas strongly affect the 2DEG properties of the heterostructure due to altering of the surface barrier accompanied by thinning of the layer structure. Depending on the layer structure and the plasma conditions used the electronic properties may be recovered by annealing.
A thermal anneal process has been developed that significantly enhances minority carrier lifetime (MCL) in bulk-grown substrates. Microwave photoconductivity decay (MPCD) measurements on bulk grown substrates subjected to this process have exhibited decay times in excess of 35 μs. Electron Beam Induced Current (EBIC) measurements indicated a minority carrier diffusion length (MCDL) of 65 μm resulting in a calculated MCL of 15 μs, well within the range of that measured by MPCD. Deep level transient spectroscopic (DLTS) analysis of samples subjected to this anneal process indicated that a significant reduction of deep level defects, particularly Z1/2, may account for the significantly enhanced lifetimes. The enhanced lifetime is coincident with a transformation of the original as-grown crystal into a strained or disordered lattice configuration as a result of the high temperature anneal process. PiN diodes were fabricated employing 350 μm thick bulk-grown substrates as the intrinsic drift region and thin p- and n-type epitaxial layers on either face of the substrate to act as the anode and cathode, respectively. Conductivity modulation was achieved in these diodes with a 10x effective carrier concentration increase over the background doping as extracted from the differential on-resistance. Significant stacking fault generation observed during forward operation served as additional evidence of conductivity modulation and underscores the importance of reducing dislocation densities in substrates in order to produce a viable bulk-grown drift layer.
The current status of SiC bulk growth is reviewed, while specific
attention is given to the effect of defects in SiC substrates and
epitaxial layers on device performance and yield. The progress in SiC
wafer quality is reflected in the achievement of micropipe densities
as low as 0.92 cm−2 for a 3-inch n-type 4H-SiC wafer, which
provides the basis for a high yielding fabrication process
of large area SiC power devices. Using a Murphy Probe Yield Analysis for the
breakdown characteristics of 10 kV PiN diodes we have extracted
an “effective” defect density for 4H-SiC material to be as low as
30 cm−2, providing valuable information to further isolate and
address the specific material defects critical for device performance.
We address the problematic degradation of the forward characteristics
(Vf-drift) of bipolar SiC PiN diodes [CITE].
The underlying mechanism due to stacking fault formation in the epitaxial
layers and possible effects of device processing are investigated.
An improved device design is demonstrated, which effectively stabilizes
this Vf-drift. We show the progression in the development of
semi-insulating SiC grown by the sublimation technique from extrinsically
doped material to high purity semi-insulating (HPSI) 4H-SiC bulk crystals of
up to 100 mm diameter without resorting to the intentional introduction
of elemental deep level dopants, such as vanadium. Uniform resistivities
in 3-inch HPSI wafers greater than 3 × 1011 Ω-cm
have been achieved. Secondary ion mass spectrometry, deep level transient
spectroscopy and electron paramagnetic resonance data suggest that the
semi-insulating behavior in HPSI material originates from deep levels
associated with intrinsic point defects. MESFETs produced on HPSI wafers
are free of backgating effects and have resulted in the best combination of
power density and efficiency reported to date for SiC MESFETs of
5.2 W/mm and 63% power added efficiency (PAE) at 3.5 GHz.
The process conditions during SiC bulk crystal growth by physical vapor transport (PVT) are studied both theoretically and experimentally focussing on the magnitude of achievable growth rates V and possible correlations with defect formation. An increase of micropipe density with crystallization rate is observed. Growth parameters determining V are identified allowing a general non-dimensional representation of the dependencies of growth rate from kinetics, mass transport and heat transfer. It can be shown that at conventional process conditions of SiC growth by sublimation in graphite environment (5 mbar ≤p≤ 100 mbar, 2400K ≤T≤ 2600K) growth is limited by diffusion and kinetics for very short crystal lengths L and by heat transfer for geometries L> 1 mm. Including possible destabilizing effects due to constitutional supercooling an augmentation of V without deteriorating crystal quality should be conducted by stochiometry control for supression of graphitization and control of the thermal field tailoring the axial heat transfer with process time. Finally SiC growth from the liquid phase is introduced to promise a growth technique for specific SiC material as, in contrast to PVT growth, the closing of micropipes is demonstrated to be feasible.
Experimental and numerical analysis have been performed on the sublimation growth process of SiC bulk crystals. Crystallographic, electrical and optical properties of the grown silicon carbide (SIC) crystals have been evaluated by various characterization techniques. Numerical models for the global simulation of SiC bulk growth including heat and mass transfer and chemical processes are applied and experimentally verified.
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