In the scribe lane, which is located at the frame neighboring two chips, most of the test patterns for monitoring electrical characteristics of memory device as well as various key patterns for photo process are formed. The pattern density of these regions is lower than that of the main chip area, and cause nitride erosion by dishing phenomena during HSS STI CMP process. Nitride erosion occurred in the scribe lane region, could the affect erosion properties of cell region in main chip area, results in within die remain nitride variation and marginal fail in device operation. In this work, in order to prevent these problems, pattern design in the scribe lane was modified so as not to occurs within die remain nitride variation. The effects of improvement in within die remain nitride variation were investigated by FIB-TEM analysis and its correlation with electrical properties were explained.