Silicon nanocrystals can be used in non-volatile memory devices to reduce susceptibility to charge loss via tunnel oxide defects, allowing scaling to smaller sizes than possible with conventional Flash memory technology. In order to optimize device performance, it is desirable to maximize the nanocrystal density and surface coverage, while maintaining sufficient inter-crystallite separation to limit electron tunneling between adjacent crystallites. Ideally, crystallite densities in excess of 1012cm-2 with relatively narrow particle size distributions must be obtained, posing a significant challenge for process development and control. In order to facilitate development of such a process, a rate-expression-based model has been developed for the nucleation and growth of silicon nanocrystals on SiO2 in a CVD process. The model addresses the phenomena of nucleation, growth, and coalescence and includes the effects of exclusion zones surrounding the growing nuclei. The model uses a phenomenological expression to describe the nucleation rate and assumes that following nucleation, crystallite growth is dominated by gas-phase deposition processes, analogous to CVD of polycrystalline silicon. The model-predicted time-evolutions of crystallite densities and crystallite size distributions are consistent with experimental distributions as measured by Scanning Electron Microscopy (SEM). By coupling the model to a reactor-scale model of polysilicon CVD, it is possible to predict variations in the crystallite size distributions at various locations across a wafer as a function of reactor settings (temperature, pressure, flow rates, etc…). This in turn can be used for process control and optimization in order to ensure uniform deposition of nanocrystals in a large-scale manufacturing environment.