Critical dimensions in advanced semiconductor devices are now such that a significant fraction of some structures is contained within the thickness of a TEM foil. An important example is the vias used in multilevel metallization to interconnect transistors and other structures. Current generation vias have a diameter of 300 nm, and vias in devices under development are targeted at 180 nm. These dimensions are to be compared to the thickness of a TEM foil, which may be ∼50 nm. Vias are typically fabricated by etching holes in a dielectric layer, then depositing into these holes a barrier metal, such as Ta, followed by a Cu seed layer and finally Cu fill. Critical to via processing reliability are the thicknesses of barrier and seed layers. A TEM cross section of such a via will contain sharply curved layers which, when seen in projection, will lead to inaccurate measurement of layer thicknesses. Ordinary plan view preparation of these vias avoids this projection problem, but uncertainty is introduced in the height at which the via is sectioned.
We have developed an angled plan view (APV) FIB preparation technique that allows accurate measurement of barrier and seed thicknesses at discrete heights from bottom to top of a via.