As the dimensions of ultralarge-scale-integration devices scale to smaller feature sizes and larger die dimensions, the resistance-capacitance (RC) delay of the metal interconnect will increasingly limit the performance of high-speed logic chips. This is because the transistor capacitance and resistance both scale to lower values as the feature size is reduced, while both the line-to-line capacitance and resistance of the metal-interconnect lines increase as their dimensions decrease. For interconnects 5-mm long, the crossover feature size at which the interconnect delay dominates the transistor delay is approximately 0.5 μm. Since this interconnect RC delay increases roughly quadratically with decreasing feature size versus the historical quadratic reduction in transistor delay, device designers currently face difficult barriers to continued performance increases with scaling. Figure 1 presents the components of the RC delay for a single-transistor/single-interconnect combination with 0.35-μm feature sizes. The total delay can be broken into four additive components: the transistor delay R
0, the interconnect delay rLcL, and the two transistor/interconnect cross terms where R
0 and C
0 are the transistor resistance and capacitance, r and c are the specific resistance and capacitance, and L is the interconnect length. As can be seen for interconnect lengths less than about 100-μm long, the intrinsic transistor delay dominates. However for interconnect lengths between approximately 100 μm and 10 mm, the resistance of the transistor coupled with the capacitance of the interconnect dominates the combined delay, resulting in a linear increase in delay with increasing line length.