Effect of the seed layer on Seebeck coefficient measurement of electroplated thermoelectric films was quantitatively analyzed. It is found that sheet, rather than bulk resistance of the seed layer, or more precisely its relative comparison to sheet resistance of the film, determines the effects. The analysis reveals that the seed layer’s effect can be neglected (within 1% error) only if the sheet resistance ratio [R□2(film)/R□1(seed)] is smaller than 0.01. This condition commonly requires film thicknesses of 100 μm or more, which is not practically relevant. Based on the analysis we proposed a new method that is applicable for 10 times thinner films. This approach for determining Seebeck coefficient is simple, and more importantly, electroplated films can be characterized in their statu nascendi. Finite element simulation and experiments verified the analysis.

Because of their superior electronic properties and bottom-up growth mode, Carbon Nanotubes (CNT) may offer a valid alternative for high aspect ratio vertical interconnects in future generations of microchips. For being successful, though, CNT based interconnects must reach sufficiently low values of resistance to become competitive with current W or Cu based technologies. This essentially means that CMOS compatible processes are needed to produce dense CNT shells of extremely high quality with almost ideal contacts. Moreover, their electrical properties must be preserved at every process step in the integration of CNT into vertical interconnect structures. In this work this latter aspect is analyzed by studying the changes in the electrical characteristics when encapsulating CNT into different oxides. Oxide encapsulation is often exploited to hold the CNT in place and to avoid snapping during a polishing step. On the other hand, oxide encapsulation can influence the properties of the grown CNT which are directly exposed to possibly harmful oxidative conditions. Two different deposition techniques and oxides were evaluated: Chemical Vapor Deposition (CVD) of SiO2 (reference) and Atomic Layer Deposition (ALD) of Al2O3 in less aggressive oxidizing conditions. The two processes were transferred to CNT interconnect test structures on 200mm wafers and electrically benchmarked. The CNT resistance was measured in function of the CNT length which allows the extraction and individual distinction of the resistive contributions of the CNT and the contacts. It is shown that the encapsulating SiO2 deposited by CVD degrades the resistance of CNT by altering their quality. Directions for future improvements have been identified and discussed.

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.

Semiconductor nanowires are attractive nano- building blocks for microelectronics. However, the requirements for their manufacturing and application in the microelectronics industry are very demanding. Beyond compatibility with Si technology, full control on the characteristics of the grown wires (diameter, location, crystallinity, etc..), homogeneity on wafer –scale and reproducibility are essential. In this study we review critically important challenges for a controlled process of In –mediated growth of Si nanowires. First, we stress the importance of surface type for both particle catalysts and growth substrates. Both selection and preparation of such surfaces have large impact on growth, as they influence the initiation and the driving forces for the VLS growth mechanism. Moreover, wire characteristics such as morphology, crystalline quality and growth orientation appear more difficult to control when growing from particles with sizes below 40-50nm. This limitation arises as a result of both fundamental mechanisms and more specific constrains linked to the In-Si system.

A few perspectives are given for the achievement of a controlled Si nanowire growth in a Si –technology compatible fashion.

The integration of high-density CNT bundles as via interconnects in a CNT/Cu-hybrid BEOL stack is evaluated. CNT via-conduits may greatly improve heat dissipation and as such lower interconnect resistance and improve electromigration resistance. Each carbon shell of the nanotube contributes to electrical and thermal conduction and densities as high as 5×1013 shells per cm2 are estimated necessary. CNT growth processes on BEOL compatible metals are presented with tube densities up to 1012cm−2 and shell densities approaching 1013 cm−2 on blanket substrates. Selective growth of CNT bundles with carbon shell densities around 1012cm−2 is demonstrated with high yield. Ohmic behavior of TiN/CNT/Ti contacts is shown with a CNT via resistivity of 1.2 mΩ cm.

Establishing a cost-effective technology for the metallization of through-Si vias (TSV) is an important factor in the realization and volume manufacturing of 3D-stacked integrated circuits (3D-SIC). Cu electroplating, which is the preferred technique, should provide not only a void-free TSV fill, but also short filling time and small overburden. The duration of the plating process is a significant contributor to the overall 3D process cost, and thus needs to be minimized. The overburden, the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the following processing steps (e.g. chemical mechanical polishing, CMP). In this paper we report on Cu plating of TSV-s with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits.

The use of Au nanoparticles as catalysts for growth of Si nanowires poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts can be broadened when the need for catalytic precursor dissociation is eliminated. However, the requirements for selective deposition in a gas phase transport -limited regime become stringent. When competing deposition of amorphous Si can bury the particles faster than the incubation time for VLS growth, no nanowire growth will be initiated. We show that the use of a catalyst such as In, already in a liquid form at the growth temperature, is effective. Therefore, the choice of VLS catalysts among the low melting point metals from the III, IV and V groups is suggested.