For graphene FETs, asymmetry in the drain current transfer characteristics has been observed. It has been proposed that asymmetry is due to additional resistances from p-n transition regions along the channel [1,2]. Calculations of the additional resistance have been received attention for small p-n transition lengths [3,4]. In this paper, we analyze the resistance of graphene FETs with p-n junctions when transition lengths are long compared with energy and momentum relaxation lengths, as is found in many experimental FETs. We employ a two dimensional device simulator to determine the electric field and channel conductivity variations in the vicinity of the FET gate, assuming rapid electron/hole equilibration. The simulations show added resistances in the range of 50-500 Ω μm p-n junction. We also extract the additional p-n resistance ΔR from experimental results by plots of Vd/Id vs. 1/|Vg-Vt|. Values of ΔR of order 450 Ω μm were extracted from FET results reported in . Epitaxial graphene FETs fabricated on a SiC substrate  gives additional resistance of 620 Ωum. Both results are in reasonable agreement with the simulations.
The physically-based device simulator Atlas of Silvaco with parameters modified for graphene was used to obtain carrier distributions. A graphene FET on SiO2 substrate with a global back gate and 0.3μm gate/drain and gate/source gaps was studied. The carrier density in the gap region was controlled by back gate bias (Vbg) while the channel region under the top gate was modulated by top and back gate simultaneously. A long channel device at Vds=10mV was used to minimize the lateral electric field effect.
From the simulated carrier distribution, we can obtain the resistivity along the channel by ρ=1/[qμ(n+p)]. Mobility is assumed to be equal for electrons and holes, and depends on carrier concentration Ns, μ=μ0 (N0/Ns)1/2 where N0 and μ0 are intrinsic carrier concentration and peak mobility, respectively. Under positive Vbg, the graphene layer becomes n-type in the gap region and channel region. Proper top gate bias (Vg) may be applied to make channel region intrinsic, p-type or n-type. Therefore, various configurations along the channel such as npn or nnn structures may be created. In the p-n transition region, the total number of carriers reduces to N0 and resistivity shows a peak. The additional resistance of a p-n junction can be calculated by integrating the difference of the resistivity vs. channel position for the nnn and npn structures. The integrated resistance value is impacted by the peak height and peak width. The peak height is controlled by Vg-Vt; the resistivity reaches a maximum at the threshold condition, where the electron and hole densities reach their intrinsic levels. The peak width is also controlled by Vg, via fringing field of the gate.