This chapter focuses on synthesis-based asynchronous controller design. Such designs use a bounded delay model, similarly to synchronous circuits. In this particular design methodology the datapath is decoupled from the control logic. Often the very same synchronous datapath can be used directly, with minor modifications.
Figure 8.1 below illustrates a synthesis-based controller in a synchronous pipeline, providing the clock (Clk) to the flip-flops. A separate synthesis-based controller can be designed uniquely for each stage of the pipeline, or a more general circuit can be specified and synthesized to fit all pipeline stages. Figure 8.1(a) illustrates a standard synchronous pipeline. In Figure 8.1(b) the Clk signal has been stripped out of the pipeline, and the controllers are placed so as to provide the latching signal for the flip-flops.
In this chapter we will first present some background on burst-mode circuits and on ways to build these controllers. We will then review approaches for building input–output circuits from signal transition graph specifications.
Fundamental-mode Huffman circuits
In the fundamental-mode style, circuits consist of a network of combinational gates that take inputs, move the circuit from one state to another, generate outputs, and also generate the next-state logic, similarly to the way in which standard synchronous circuits operate. The next-state outputs feed back through the delay elements and arrive at the inputs of the controller as the current state. Sometimes delays on feedback paths are necessary, however, they are not shown explicitly in Figure 8.2.