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This paper presents a circuit architecture for a new integrated on chip test method for microwave circuits. The proposed built-in-self-test (BIST) cell targets a direct low-cost measurement technique of the gain and the 1 dB input compression point (CP1) of a K-band satellite receiver in the 18–22 GHz frequency bandwidth. A signal generator at the radiofrequency (RF) front end input of the device under test (DUT) has been integrated on the same chip. To inject this RF signal, a loopback technique has been used and the design has been accommodated for it. This paper focuses on the design of the most sensitive block of the BIST circuit, i.e. the RF signal generator. This circuit, fabricated in a SIGe:C BiCMOS process, consumes 10 mA. It presents a dynamic power range of 17 dB (−41; −24 dBm) and operates in a frequency range of 5.6 GHz (17.5; 23 GHz). This BIST circuit gives new perspectives in terms of test strategy, cost reduction, and measurement accuracy for microwave-integrated circuits and could be adapted for mm-wave circuits.
In this paper, the design and the measurements of three-dimensional through silicon vias (TSVs) based-integrated solenoids embedded within high-resistive silicon is presented. Prior to silicon implementation, a rigorous theoretical analysis is proposed to put in obviousness the advantages of using such coil architecture for L and S band applications. This analysis, demonstrates a clear reduction of the footprint passive function lying on the external substrate together with a reduced capacitive coupling with the local environment. Two-port radio frequency measurements have been performed in a wide-frequency range (100 MHz – 50 GHz) in order to support the theoretical investigations. Solenoids exhibit high-quality factors below 4 GHz – Q = 25 @ 2 GHz for a 800 pH device – and clearly outperforms classical planar architecture considered in most of the integrated circuit processes. Two different modeling approaches (compact modeling and EM modeling) are then proposed in order to speed-up their design implementation in a typical CAD design flow. Based on the available data, a good agreement is shown between and simulated data.
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