The melt kinetics of shallow junction formation by laser thermal processes has been studied using transient conductance measurements. The melt and solidification dynamics of 20 nm amorphous layers were measured and shown to follow behaviors predicated by deeper melts, including explosive crystallization and interface bounce back. The effects of surface barrier oxides and metal absorber layers, required for CMOS process integration, were examined and shown to be nearly negligible. Quantitative evaluation of a device process window by these measurements was in good agreement with sheet resistance results. Finally, the effect of the buried oxide in SOI structures was investigated. Solidification velocities in such structures were reduced by a factor of three as compared with bulk silicon.