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We present here a reactive ion etching recipe to fabricate germanium nanowires.
We used a combination of Cl2, N2 and O2 and
studied the influence of both the gas pressure and the O2 mass flow
on the morphology of the nanowires. 5 µm long nanowires with an aspect
ratio of 20 are demonstrated with smooth surfaces and a tapering below 20
nm/µm. We also show that both gold and aluminum can be used as hard
mask; the latter achieving a selectivity with germanium above 100.
The authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.
We report the growth of silicon nanowires (SiNWs) by chemical vapor deposition (CVD) with several catalysts. We performed low temperature photoluminescence (PL) experiments on as-grown SiNWs for the following catalysts: Au, Cu, TiSi, PdSi and PtSi. Nanowires are chemically treated with an aqua regia solution to remove the catalyst droplets, this step is followed by a thermal oxidation process. We compared the PL of as-grown and processed SiNWs for each catalyst.
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