Highly dense next generation dynamic random access memory (DRAM) devices impose severe restrictions on the times, temperatures and atmospheres of all thermal process steps following the sourcedrain implantation. BPSG reflow and source-drain implant activation are two of the process steps that contribute significantly towards enhanced overall thermal budget during the fabrication of DRAM devices.
In this paper, we present the results of an optimized thermal budget process using a combination of steam reflow and rapid thermal annealing (RTA). We demonstrate that this approach produces better reflow characteristics than the best RTA or reflow cycle alone. The processes will be compared on pchannel CMOS devices and the differences in various electrical characteristics will be highlighted. The results of BPSG reflow and dopant outdiffusion will be presented. Experimentally obtained data on junction depth from SIMS analysis will be correlated with corresponding RTA simulation results.