We have found that the surface morphology of GaAs grown on Si by MBE is smoother at lower growth temperatures (<500° C), but that the crystalline properties improve at higher growth temperatures (575-600°C). After thermal annealing at 850°C for 15 rai the TEM plan-views indicate that the dislocation density on the surface is reduced by a factor of 4 only. However, the TEM cross-sections indicate a much larger reduction of dislocations in highly dislocated regions near the GaAs/Si interface. Dislocations which are loops or tangles tend to shrink and clean up after annealing leaving a larger volume of GaAs free from, or with fewer, dislocations. The density of electron deep levels reduces with increasing thickness. Electron traps M1, M3 and M4 are not seen when a high purity As is used. For high device performance, the GaAs buffer layer thickness should be at least 2 µm. Although the wafer warpage increases from 7 µm to 52 µm as the GaAs thickness increases from 1.2 µm to 4.2 µm on 7.5 cm wafers, the wafers are as fiat as the original Si wafers under vacuum clamping. Wafer warpage reduced significantly when GaAs was grown selectively through a Si shadow mask. For 1 µm gate MESFET's, σvT was 65 mV on a 3.5 × 3 cm2 wafer area with gmax = 153 mS/ram. A minimum propagation delay of 52 ps/stage at a power dissipation of 1.3 mW/gate was measured for the 19 stage DCFL ring oscillators with 40= yield. Conductivity of the Si substrate and GaAs buffer layer posed no problem in channel isolation. The divide-by-two circuits performed the frequency dividing operation up to 1.8 GHz. The study shows that GaAs-on-Si has a great potential for digital IC's.