This paper addresses an important process issue in tie integration of chemical mechanical polishing (CMP) with interlayer dielectric (ILD) deposition for advanced back end processing. Gap fill between metal lines is achieved by using a dep-etch-dep technique for the tetraethylorthosilicate (TEOS) ILD deposition. The ILD layer is then planarized by CMP. Vias are etched through the ILD and filled with tungsten plugs in a blanket tungsten deposition and tungsten CMP sequence. Delamination has been observed at the interface between the TEOS layers following the blanket tungsten deposition and before or during tungsten CMP. The weak interface between the TEOS layers was found to be the result of residual carbon and fluorine from the tetraflouromethane (CF4) doped etch process. The interface between the TEOS layers was examined using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Experiments were carried out to determine if the residue and subsequent delamination could be eliminated by modifying the dep-etch-dep process. An improved process was identified and has been implemented on a 0.5μm CMOS and mixed-mode BiCMOS production line with no subsequent occurrence of interfacial delamination.