Because of their superior electronic properties and bottom-up growth mode, Carbon Nanotubes (CNT) may offer a valid alternative for high aspect ratio vertical interconnects in future generations of microchips. For being successful, though, CNT based interconnects must reach sufficiently low values of resistance to become competitive with current W or Cu based technologies. This essentially means that CMOS compatible processes are needed to produce dense CNT shells of extremely high quality with almost ideal contacts. Moreover, their electrical properties must be preserved at every process step in the integration of CNT into vertical interconnect structures. In this work this latter aspect is analyzed by studying the changes in the electrical characteristics when encapsulating CNT into different oxides. Oxide encapsulation is often exploited to hold the CNT in place and to avoid snapping during a polishing step. On the other hand, oxide encapsulation can influence the properties of the grown CNT which are directly exposed to possibly harmful oxidative conditions. Two different deposition techniques and oxides were evaluated: Chemical Vapor Deposition (CVD) of SiO2 (reference) and Atomic Layer Deposition (ALD) of Al2O3 in less aggressive oxidizing conditions. The two processes were transferred to CNT interconnect test structures on 200mm wafers and electrically benchmarked. The CNT resistance was measured in function of the CNT length which allows the extraction and individual distinction of the resistive contributions of the CNT and the contacts. It is shown that the encapsulating SiO2 deposited by CVD degrades the resistance of CNT by altering their quality. Directions for future improvements have been identified and discussed.

We investigate the structural, optical and electrical properties of single-layer graphene exposed to oxygen plasma treatment. We find that the pristine semimetallic behavior of graphene disappears upon plasma treatment, in favour of the opening of a bandgap and the featuring of semiconducting properties. The metal-to-semiconductor transition observed appears to be dependent on the plasma treatment time. The semiconducting behavior is also confirmed by photoluminescence measurements. The opening of a bandgap in graphene is explained in terms of graphene surface functionalization with oxygen atoms, bonded as epoxy groups. Ab initio calculations of the density of states show more details about the oxygen–graphene interaction and its effects on the graphene optoelectronic properties, predicting no states near the Fermi level at increasing epoxy group density. The structural changes are also monitored by Raman spectroscopy, showing the progressive evolution of the sp2 character of pristine graphene to sp3, due to the lattice decoration with out-of-plane epoxy groups.

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.

Semiconductor nanowires are attractive nano- building blocks for microelectronics. However, the requirements for their manufacturing and application in the microelectronics industry are very demanding. Beyond compatibility with Si technology, full control on the characteristics of the grown wires (diameter, location, crystallinity, etc..), homogeneity on wafer –scale and reproducibility are essential. In this study we review critically important challenges for a controlled process of In –mediated growth of Si nanowires. First, we stress the importance of surface type for both particle catalysts and growth substrates. Both selection and preparation of such surfaces have large impact on growth, as they influence the initiation and the driving forces for the VLS growth mechanism. Moreover, wire characteristics such as morphology, crystalline quality and growth orientation appear more difficult to control when growing from particles with sizes below 40-50nm. This limitation arises as a result of both fundamental mechanisms and more specific constrains linked to the In-Si system.

A few perspectives are given for the achievement of a controlled Si nanowire growth in a Si –technology compatible fashion.

The integration of high-density CNT bundles as via interconnects in a CNT/Cu-hybrid BEOL stack is evaluated. CNT via-conduits may greatly improve heat dissipation and as such lower interconnect resistance and improve electromigration resistance. Each carbon shell of the nanotube contributes to electrical and thermal conduction and densities as high as 5×1013 shells per cm2 are estimated necessary. CNT growth processes on BEOL compatible metals are presented with tube densities up to 1012cm−2 and shell densities approaching 1013 cm−2 on blanket substrates. Selective growth of CNT bundles with carbon shell densities around 1012cm−2 is demonstrated with high yield. Ohmic behavior of TiN/CNT/Ti contacts is shown with a CNT via resistivity of 1.2 mΩ cm.

Gaseous impurities in the chamber of a SHS2800ε rapid thermal processor were quantitatively measured by using atmospheric pressure ionisation mass spectrometry (APIMS). APIMS is a very sensitive technique to detect trace impurities in a bulk (1 atm) gas. A wide dynamic range (0.1 ppb - 10 ppm) measurement was successfully performed, which allowed in-situ monitoring of impurities during RTP. This work reports the fundamental behaviour of ambient impurities originating from different sources. The sources discussed in this paper are threefold: system background, wafer loading, and the wafer itself. Ambient management requires a better understanding of the independent contribution of each source on processing.

It is found that Fe in a ppb level Fe-spiked SC1 solution precipitates in-homogenous. The local high iron concentrations are difficult to rinse, create micro-roughness, and induce weak spots in capacitors. With AFM it has been shown that rings of 3–8 μm are etched in the silicon and that the etch products (silicates) are deposited on one side just outside the ring. The capacitor yield loss induced by this SC1 treatment can not be recovered fully by a subsequent SC2 or dHCL step, while a dHF/dHCl does fully recover the yield and removes the iron and silicate rim.