Rapid thermal epitaxy (RTE) is studied for a variety of applications including transistors as well as optoelectronic devices. Two transistor applications are discussed here. First, the growth of n-type epitaxial layers over n+ buried layers for low power BiCMOS, and second, the growth and fabrication of charge injection transistors (CHINTs) from a multi-layer structure including strained Si1−xGex layers.
Scaled bipolar transistors for BiCMOS integrated circuits require low collector-substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector-substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic buried layer implant dose, and pre-epitaxial bake temperature on autodoping using RTE. To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be linearly dependent on the growth rate (i.e. low growth rates trap less arsenic at the substrate/epi layer interface). Next, by adjusting the pre-bake temperature over a range from 800 to 1050°C without changing the growth conditions, we first observed a rise in autodoping with temperature to 950°C at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature pre-bake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic doped buried layers for low power BiCMOS are possible.
Charge injection transistors and logic elements have been successfully implemented in a Si/Si0.7Ge0.3 heterostructure grown by RTE on a Si substrate. Shallow p+ source and drain ohmic contacts are obtained by a boron diffusion from a selectively deposited boron doped Ge layer. Room temperature operation of the charge injection transistor is demonstrated for the first time. High frequency measurements indicate a short circuit current gain cutoff frequency of 6 GHz.