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The effect of iron contamination in silicon on the properties of thermally grown thin oxides is studied through electrical modelling and experimental MOSDOT testing. Iron concentration is measured using a surface photovoltage / diffusion length technique. Failure mechanisms related to iron contamination are proposed. Contamination limits for various gate oxide thicknesses are defined. Experimental results show that reduction of oxide thickness from 20nm to lOnm requires a reduction in iron conntamination by 100 times.
Infrared absorption and Raman scattering measurements of SIMOX structures implanted at various temperatures yield information on the structure and the strain in both the top silicon and the buried oxide layers. Both techniques can also be used to monitor the implant temperature after the implantation.
We present fast, wafer-scale imaging of the surface charge achieved via non-contact measurement of the surface potential barrier by surface photovoltage (SPV) under high excitation levels. The approach is capable of resolving surface charge differences as small as 108 q/cm2. Fundamentals of surface charge imaging are discussed, and the method is compared with standard SPV contamination mapping. Examples include problems relevant to silicon IC fabrication and surface charge maps of GaAs and InP.
The effects of iron contamination on gate oxide characteristics are examined from an experimental and modeling perspective. Gate oxide integrity is measured for silicon wafers contaminated with 1010 to 1014cm−3 of iron. Thermal oxides of 8, 10,13 and 20nm are studied. Iron concentration in silicon is measured non-destructively using Surface Photovoltage (SPV) minority carrier lifetime analysis. The SPV analysis technique is described. Based on the experimental data, allowable threshold iron contamination levels for various gate oxide thicknesses are established. For 10nm oxides, iron concentration cannot exceed 8×1010cm−3 without severe degradation in oxide quality. The threshold contamination level for 20nm oxides is 200 times higher. Time dependent dielectric breakdown (TDDB) test results indicate detrimental reliability effects can occur at even lower contamination levels.
To monitor the effectiveness of standard cleaning processes in semiconductor manufacturing, suitable diagnostic procedures must be found. In addition the procedures must be non-contact and non-destructive. Increasingly the techniques of surface photovoltage and surface charge imaging together are finding applications as in-line wafer monitors. This talk will discuss how they are being used to monitor the quality of surface cleaning processes. We will show that if unchecked the "clean" may actually contribute contamination.
Surface photovoltage (SPV) measurements of lifetime and charge are used by the silicon industry for real-time, non-contact monitoring of alkalide and heavy metal contamination during IC processing. Information about contamination present at the surface or in the bulk of a silicon wafer is derived from their effects on measured electronic characterization. Identification and detection, with a sensitivity of ppq (107 cm'3), of Fe and Cr in the bulk of p-type silicon is possible via monitoring of their decomposition/pairing kinetics with boron. We will show the most important examples of the application of SPV to monitor critical IC processing steps. The allowable contamination thresholds in IC processing lines are a very strong function of technology and are different for various metals.
In-line monitoring of the electrical properties of high-k dielectrics in logic or memory fab-lines has become increasingly important in the semiconductor industry. Non-contact corona-Kelvin based metrology can be used to affectively monitor in-line key dielectric properties. Furthermore, we present an important extension of this metrology to the micro-scale that allows measurement of dielectric properties on test sites as small as 40μm × 70μm. This is achieved through miniaturization of the corona charging apparatus and of the Kelvin probe without a sacrifice in precision or repeatability. Corona-Kelvin micro-metrology allows for the monitoring of the critical dielectric properties directly on product wafers that can then be returned to the fab-line for continued processing. Application examples are given for dielectric capacitance of advanced dielectrics and for the properties of an oxide-nitride-oxide (ONO) memory structure. In the latter case we demonstrate programming and erasing of the ONO structure realized by corona charging. We also use the measured flatband voltage and total charge to identify the location of the programmed charge at the first SiO2/Si3N4 interface in the ONO structure.
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